Neural network unit with neural memory and array of neural processing units that collectively shift row of data received from neural memory

A processor, comprising:

• an instruction set having architectural instructions that instruct the processor to perform actions;
• and an array of N processing units (PU) each having:
• an accumulator having an output;
• an arithmetic unit having first, second and third inputs and that performs an operation thereon to generate a result to store in the accumulator, the first input receives the output of the accumulator;
• a weight input that is received by the second input to the arithmetic unit;
• and a multiplexed register having first and second data inputs, an output received by the third input to the arithmetic unit, and a control input that controls selection of the first and second data inputs;
• and the output of the multiplexed register is also received by the second data input of the multiplexed register of an adjacent PU, the multiplexed registers of the N PUs collectively operate as an N-word rotater when the control input specifies the second data input;
• a first memory that holds W rows of N weight words and provides the N weight words of a row of the W rows to the corresponding weight inputs of the N PUs of the PU array;
• and a second memory that holds D rows of N data words and provides the N data words of a row of the D rows to the corresponding first data inputs of the multiplexed register of the N PUs of the PU array.

A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising:

• computer usable program code embodied in said medium, for specifying an apparatus, the computer usable program code comprising:
• first program code for specifying an array of N processing units (PU) each having:
• an accumulator having an output;
• an arithmetic unit having first, second and third inputs and that performs an operation thereon to generate a result to store in the accumulator, the first input receives the output of the accumulator;
• a weight input that is received by the second input to the arithmetic unit;
• and a multiplexed register having first and second data inputs, an output received by the third input to the arithmetic unit, and a control input that controls selection of the first and second data inputs;
• and the output of the multiplexed register is also received by the second data input of the multiplexed register of an adjacent PU, the multiplexed registers of the N PUs collectively operate as an N-word rotater when the control input specifies the second data input;
• second program code for specifying a first memory that holds W rows of N weight words and provides the N weight words of a row of the W rows to the corresponding weight inputs of the N PUs of the PU array;
• and third program code for specifying a second memory that holds D rows of N data words and provides the N data words of a row of the D rows to the corresponding first data inputs of the multiplexed register of the N PUs of the PU array.