System and method for improving peripheral component interface express bus performance in an information handling system

An information handling system (IHS) comprising:

• a processor communicatively coupled to a system memory;
• a first peripheral component interconnect express (PCIe) device;
• a second PCIe device that includes duplicate data of the first PCIe device;
• and
• a hardware logic device communicatively coupled to the processor and to each of the first PCIe device and the second PCIe device, the hardware logic device having control logic that facilitates data transmission, wherein the control logic causes the hardware logic device to:
• detect a first mastered memory transaction request from the first PCIe device to the system memory, the first mastered memory transaction request including a first system memory address;
• detect a second mastered memory transaction request from the second PCIe device to the system memory, the second mastered memory transaction request including a second system memory address;
• wherein the hardware logic device comprises a root port serving each PCIe device, and the first and second mastered memory transaction requests comprise transaction layer packets (TLPs) that are detected at respective root ports of the FPGA;
• determine if the first system memory address and the second system memory address are the same system memory address;
• in response to the first system memory address and the second system memory address being the same system memory address, coalesce the first memory transaction request and the second memory transaction request into a common memory transaction request;
• and
• issue the common memory transaction request to the system memory.

A method of transmitting data in an information handling system (IHS) configured with a plurality of a peripheral component interconnect express (PCIe) devices, the method comprising:

• detecting, via a hardware logic device, a first PCIe transaction request issued from the IHS to a first PCIe device;
• in response to detecting the first PCIe transaction request, generating, via the hardware logic device, a second PCIe transaction request for a second PCIe device, the second PCIe transaction request being a duplicate of the first PCIe transaction request;
• issuing the first PCIe transaction request to the first PCIe device;
• and
• issuing the second PCIe transaction request to the second PCIe device.

An information handling system (IHS) comprising:

• a processor communicatively coupled to a system memory;
• a hardware logic device communicatively coupled to the processor;
• a first peripheral component interconnect express (PCIe) device communicatively coupled to the hardware logic device;
• and
• a second PCIe device communicatively coupled to the hardware logic device;
• wherein the hardware logic device includes control logic thereon that causes the hardware logic device to:
• detect a first PCIe transaction request issued from the IHS to a first PCIe device;
• in response to detecting the first PCIe transaction request, generate a second PCIe transaction request for a second PCIe device, the second PCIe transaction request being a duplicate of the first PCIe transaction request;
• issue at least one single PCIe transaction request from among the first PCIe transaction request to the first PCIe device and the second PCIe transaction request to the second PCIe device, based on loading.