Memory device communicating with system on chip through at least two channels, electronic device including the same, and operating method of electronic device

A memory device comprising:

• a memory cell array including a first memory cell area and a second memory cell area;
• a first peripheral circuit configured to access the first memory cell area, in response to a first command transmitted from a system on chip (SoC) through a first channel;
• and
• a second peripheral circuit configured to access the second memory cell area, in response to a second command transmitted from the SoC through a second channel,
• wherein the first peripheral circuit includes first data input/output pins, the first peripheral circuit configured to exchange first data with the SoC by inputting or outputting the first data through the first input/output pins,
• wherein the second peripheral circuit includes second data input/output pins, the second peripheral circuit configured to exchange second data with the SoC by inputting or outputting the second data through the second input/output pins,
• wherein the first peripheral circuit and the second peripheral circuit are configured such that the first channel has a first bandwidth, the second channel has a second bandwidth, and the first and second bandwidths are different,
• wherein the first peripheral circuit further includes a first row decoder configured to select a first word line of the first memory cell area and a first column decoder configured to select a first column select line of the first memory cell area, and
• wherein the second peripheral circuit further includes a second row decoder configured to select a second word line of the second memory cell area and a second column decoder configured to select a second column select line of the first memory cell area.

An operating method of an electronic device comprising a memory device and a system on chip (SoC) communicating with the memory device, the method comprising:

• assigning a first memory cell area of the memory device to a first channel between the SoC and the memory device and assigning a second memory cell area of the memory device to a second channel between the SoC and the memory device;
• performing first data input/output between the SoC and the memory device, based on a first command transmitted to the memory device from the SoC through the first channel;
• and
• performing second data input/output between the SoC and the memory device, based on a second command transmitted to the memory device from the SoC through the second channel,
• wherein the first channel has a first bandwidth, the second channel has a second bandwidth, and the first and second bandwidths are different, and
• wherein the memory device includes:
• a first row decoder configured to select a first word line of the first memory cell area;
• a first column decoder configured to select a first column select line of the first memory cell area;
• a second row decoder configured to select a second word line of the second memory cell area;
• and
• a second column decoder configured to select a second column select line of the second memory cell area.