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US 10,474,584 B2Granted
Storing cache metadata separately from integrated circuit containing cache controller
AssigneeHewlett Packard Enterprise Development LP
InventorsJichuan Chang, Justin James Meza, Parthasarathy Ranganathan
Life of this patent
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Abstract
A technique includes using a cache controller of an integrated circuit to control a cache including cached data content and associated cache metadata. The technique includes storing the metadata and the cached data content off of the integrated circuit and organizing the storage of the metadata relative to the cached data content such that a bus operation initiated by the cache controller to target the cached data content also targets the associated metadata.
Claims22
A method comprising:
- using a cache controller to control a cache comprising cached data content and associated cache metadata, wherein the cached data content represents data content stored in a first memory, and the cache metadata comprises cache tags for the associated cached data content;
- storing the cache metadata and the cached data content in a second memory that is separate from an integrated circuit that contains the cache controller;
- generating cycles on a memory bus coupled to the first memory and the second memory to control access to the first memory and the second memory;
- and
- organizing the storage of the metadata relative to the cached data content such that a given cycle of the cycles generated on the memory bus targets the cached data content and also targets the associated metadata.
2 more elements
An apparatus comprising:
- a primary data store comprising non-volatile memory;
- a cache data store for the primary data store comprising volatile memory, wherein the cache data store comprises cached data content and cache metadata associated with the cached data content, and the cache metadata comprises cache tags for the associated cached data content;
- a memory bus coupled to the primary data store and the cache data store;
- a cache controller of an integrated circuit separate from the cache data store to initiate a bus cycle on the memory bus to concurrently target the cached data content and the associated metadata such that the non-volatile memory and the volatile memory respond to the bus cycle generated on the memory bus.
1 more element
An apparatus comprising:
- an integrated circuit comprising a cache controller, a buffer to store a pending memory access request and a first cache to store cached metadata associated with cache metadata stored in a second cache external to the integrated circuit, wherein the cache controller is adapted to, in response to the request, determine whether a cache miss occurs for the first cache and based on the determination, selectively speculatively fetch data from a primary data store external to the integrated circuit, wherein the cache metadata and the data fetched from the primary data store are arranged such that the primary data store and the second cache each furnish data in response to a memory bus cycle that targets the primary data store and the second cache.
Dependencies are inferred from the claim text.