Apparatuses and methods for cache operations

An apparatus, comprising:

• a cache controller coupled to a memory device to execute a command for cache operations, wherein the memory device comprises:
• a first subset of a plurality of subarrays of memory cells;
• a second subset of the plurality of subarrays of memory cells;
• sensing circuitry selectably coupled to the first and second subsets, the sensing circuitry including a sense amplifier and a compute component coupled to a respective sense line of the first subset;
• and
• an I/O line shared by the second subset and the sensing circuitry of the first subset, the I/O line configured to selectably couple to the sensing circuitry of the first subset to enable movement of a data value stored in the second subset to the sensing circuitry of a selected subarray in the first subset;
• wherein:
• the cache controller is configured to direct performance of a compute operation on the data value in the sensing circuitry of the selected subarray in the first subset using the compute component as a one bit processing element to perform a one bit compute operation on the data value;
• the first subset of the plurality of subarrays is a number of subarrays of two transistor and two capacitor (2T2C) dynamic random access memory (DRAM) cells configured to enable performance of processing-in-memory (PIM) operations;
• and
• the second subset of the plurality of subarrays is a number of subarrays of one transistor and one capacitor (1T1C) DRAM cells not configured to enable performance of PIM operations.

An apparatus, comprising:

• a cache controller coupled to a memory device, wherein the memory device comprises:
• a first subset of a plurality of subarrays of memory cells;
• a second subset of the plurality of subarrays of memory cells;
• a plurality of partitions, wherein each partition of the plurality of partitions includes a subarray from the respective first subset and a subarray from the respective second subset;
• sensing circuitry coupled to the first and second subsets, the sensing circuitry including a sense amplifier and a compute component coupled to a respective sense line of a plurality of sense lines for the first subset;
• an I/O line shared by the partitions and comprising a plurality of portions;
• and
• isolation circuitry configured to selectably connect a first portion of the plurality of portions of the I/O line with a second portion of the I/O line, wherein the first portion corresponds to a first partition of the plurality of partitions and the second portion corresponds to a second partition of the plurality of partitions;
• and wherein:
• the cache controller is configured to selectably direct the isolation circuitry to disconnect the first portion of the I/O line from the second portion of the I/O line during parallel directed data movements;
• a first directed data movement is within the first partition and a second directed data movement is within the second partition;
• a third directed data movement is, via the first portion of the I/O line, from a first subarray in the first subset, subsequent to performance of an operation by sensing circuitry of the first subarray on a first data value, to a first subarray in the second subset;
• a fourth directed data movement is, via the second portion of the I/O line, from a second subarray in the first subset, subsequent to performance of an operation by sensing circuitry of the second subarray on a second data value, to a second subarray in the second subset;
• and
• the third directed data movement is within the first partition and the fourth directed data movement is within the second partition.

A method for operating a memory device, comprising:

• sensing a data value in a selected first row of a selected first subarray in the memory device using a first sensing component stripe including a sense amplifier, and not including a compute component, that is selectably coupled to the selected first row;
• moving the sensed data value to a second sensing component stripe coupled to a selected second subarray, wherein the selected second subarray includes a quantity of memory cells in a column that is at most half of a quantity of memory cells in a column of the selected first subarray;
• and
• performing a compute operation on the sensed data value using a compute component as a one bit processing element to perform a one bit compute operation on the sensed data value in the second sensing component stripe coupled to the selected second subarray, wherein the second sensing component stripe includes a sense amplifier, coupled to the compute component, that is selectably coupled to a row of the selected second subarray.