Utilization-based throttling of hardware prefetchers

A method, comprising:

• fetching, by a cache memory, information from a memory for use by a processor core;
• issuing, by a prefetch circuit, a prefetch request for information from the memory to store in the cache memory using a predicted address;
• over a particular time interval:
• determining, by the prefetch circuit, a utilization value using a number of fetch requests by the cache memory and a number of prefetch requests by the prefetch circuit;
• and
• determining, by the prefetch circuit, an accuracy value using the number of prefetch requests from the prefetch circuit and a number of cache hits to prefetched information in the cache memory;
• and
• disabling, by the prefetch circuit, prefetch requests from the memory for a subsequent time interval in response to a determination that at least one of the utilization value and the accuracy value satisfies a respective threshold value.

An apparatus, comprising:

• a prefetch issue circuit configured to issue a prefetch request for information from a memory to store in a cache memory using a predicted address;
• a utilization monitor circuit configured to, over a particular time interval, determine a utilization value using a number of fetch requests by the cache memory and a number of prefetch requests issued by the prefetch issue circuit;
• an accuracy monitor configured to determine an accuracy value for issued prefetch requests over the particular time interval, and
• a prefetch throttle circuit configured to disable the prefetch issue circuit for a subsequent time interval, in response to a determination that at least one of the utilization value and the accuracy value satisfies a respective threshold value.