Cache-based communication between execution threads of a data processing system

A data processing system for providing a hardware-accelerated virtual link buffer, the data processing system comprising:

• a first cache accessible by a first processing device;
• a second cache accessible by a second processing device;
• and
• an interconnect structure that couples the first cache and the second cache, the interconnect structure comprising a link controller;
• where the first cache is configured to store a plurality of data elements produced by the first processing device in a producer cache line;
• where the link controller comprises hardware configured to transfer data elements in the producer cache line to a consumer cache line in the second cache;
• and
• where the second cache is configured to access a consumer cache line to provide the plurality of data elements, produced by the first processing device, to the second processing device;
• the data processing system further comprising a first cache controller, where the plurality of data elements are produced in sequence, where a data element of the plurality of data elements is stored at a location in the producer cache line indicated by a store position indicator, where the store position indicator is stored at a predetermined location in the producer cache line and where the first cache controller is configured to access the store position indicator.

A method for providing a virtual link buffer between a producer processing device and a consumer processing device in a data processing system, the method comprising:

• allocating a first virtual address for identifying a cache line in a cache of the producer processing device;
• allocating a second virtual address for identifying a cache line in a cache of the consumer processing device;
• storing, by the producer processing device, one or more data elements in a first cache line of the producer processing device, the first cache line identified by the first virtual address;
• transferring, by a link controller in an interconnect structure that couples the producer and consumer processing devices, the one or more data elements in the first cache line to a second cache line in the cache of the consumer processing device, the second cache line identified by the second virtual address;
• and
• loading, by the consumer processing device, the one or more data elements from the second cache line,
• where storing, by the producer processing device, a data element of the one or more data elements in the first cache line of the producer processing device comprises:
• reading a store position indicator from a designated location in the first cache line;
• storing the data element at a location in the first cache line indicated by the store position indicator;
• and
• updating the store position indicator in the first cache line.

A method for providing a virtual link buffer between a producer processing device and a consumer processing device in a data processing system, the method comprising:

• allocating a first virtual address for identifying a cache line in a cache of the producer processing device;
• allocating a second virtual address for identifying a cache line in a cache of the consumer processing device, where the second virtual address is associated with the first virtual address;
• receiving a first cache line associated with the first virtual address from the producer processing device, the first cache line comprising one or more data elements stored by the producer processing device, the first cache line identified by the first virtual address;
• determining the second virtual address associated with the first virtual address;
• and
• transferring the first cache line with the second virtual address to the consumer processing device,
• where the cache of the producer processing device comprises a level one (L1) cache and is not shared with the consumer processing device;
• and
• where the cache of the consumer processing device comprises an L1 cache and is not shared with the producer processing device.