System recovery using a failover processor
AssigneeOracle International Corporation
InventorsChristopher West, James Baer
Life of this patent
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Abstract
Techniques for system recovery using a failover processor are disclosed. A first processor, with a first instruction set, is configured to execute operations of a first type; and a second processor, with a second instruction set different from the first instruction set, is configured to execute operations of a second type. A determination is made that the second processor has failed to execute at least one operation of the second type within a particular period of time. Responsive to determining that the second processor has failed to execute at least one operation of the second type within the particular period of time, the first processor is configured to execute both the operations of the first type and the operations of the second type.
Claims18
One or more non-transitory machine-readable media string instructions which, when executed by one or more processors, cause:
- configuring a first processor, with a first instruction set, to execute operations of a first type;
- configuring a second processor, with a second instruction set different from the first instruction set, to execute operations of a second type,
- wherein the first processor is a general-purpose processor, the second processor is a digital signal processing (DSP) processor, and operations of the second type comprise floating point operations;
- determining that the second processor has failed to execute at least one operation of the second type within a particular period of time;
- and
- responsive to determining that the second processor has failed to execute at least one operation of the second type within the particular period of time:
- configuring the first processor to execute the operations of the first type and the operations of the second type.
One or more non-transitory machine-readable media storing instructions which, when executed by one or more processors, cause:
- configuring a first processor, with a first instruction set, to execute operations of a first type;
- configuring a second processor, with a second instruction set different from the first instruction set, to execute operations of a second type,
- wherein the first processor and the second processor are used to control a mechanical component;
- determining that the second processor has failed to execute at least one operation of the second type within a particular period of time;
- responsive to determining that the second processor has failed to execute at least one operation of the second type within the particular period of time:
- configuring the first processor to execute the operations of the first type and the operations of the second type,
- stopping operation of a motor of the mechanical component,
- reinitializing the component, and
- resuming operation of the motor after configuring the first processor to execute the operations of the second type.
A system comprising:
- at least one device including a hardware processor;
- the system being configured to perform operations comprising:
- configuring a first processor, with a first instruction set, to execute operations of a first type;
- configuring a second processor, with a second instruction set different from the first instruction set, to execute operations of a second type,
- wherein the first processor is a general-purpose processor, the second processor is a digital signal processing (DSP) processor, and operations of the second type comprise floating point operations;
- determining that the second processor has failed to execute at least one operation of the second type within a particular period of time;
- and
- responsive to determining that the second processor has failed to execute at least one operation of the second type within the particular period of time:
- configuring the first processor to execute the operations of the first type and the operations of the second type.
A system comprising:
- at least one device including a hardware processor;
- the system being configured to perform operations comprising:
- configuring a first processor, with a first instruction set, to execute operations of a first type;
- configuring a second processor, with a second instruction set different from the first instruction set, to execute operations of a second type,
- wherein the first processor and the second processor are used to control a mechanical component;
- determining that the second processor has failed to execute at least one operation of the second type within a particular period of time;
- responsive to determining that the second processor has failed to execute at least one operation of the second type within the particular period of time:
- configuring the first processor to execute the operations of the first type and the operations of the second type,
- stopping operation of a motor of the mechanical component,
- reinitializing the component, and
- resuming operation of the motor after configuring the first processor to execute the operations of the second type.
A method comprising:
- configuring a first processor, with a first instruction set, to execute operations of a first type;
- configuring a second processor, with a second instruction set different from the first instruction set, to execute operations of a second type,
- wherein the first processor is a general-purpose processor, the second processor is a digital signal processing (DSP) processor, and operations of the second type comprise floating point operations;
- determining that the second processor has failed to execute at least one operation of the second type within a particular period of time;
- and
- responsive to determining that the second processor has failed to execute at least one operation of the second type within the particular period of time:
- configuring the first processor to execute the operations of the first type and the operations of the second type,
- wherein the method is performed by at least one device comprising a hardware processor.
A method comprising:
- configuring a first processor, with a first instruction set, to execute operations of a first type;
- configuring a second processor, with a second instruction set different from the first instruction set, to execute operations of a second type,
- wherein the first processor and the second processor are used to control a mechanical component;
- determining that the second processor has failed to execute at least one operation of the second type within a particular period of time;
- responsive to determining that the second processor has failed to execute at least one operation of the second type within the particular period of time:
- configuring the first processor to execute the operations of the first type and the operations of the second type,
- stopping operation of a motor of the mechanical component,
- reinitializing the component, and
- resuming operation of the motor after configuring the first processor to execute the operations of the second type,
- wherein the method is performed by at least one device comprising a hardware processor.
Dependencies are inferred from the claim text.