Simultaneous multi-processor apparatus applicable to achieving exascale performance for algorithms and program systems

A apparatus, comprising:

• a Data Processor Chip (DPC), comprising:
• A. Npem programmable execution modules (PEMs), each of said PEMs including Ncore-per-module cores and a module communication interface (stairway) adapted to support communication into and out of an internal network at a sustainable data bandwidth of about Knum numbers each of Bnum bits for each of Nchannels of a channel on each local clock cycle with a clock period of Tclock,
• where said Npem is a member of a first group consisting of 9 to 144,
• where Ncore-per-module is a member of a second group consisting of 1 to 10, and
• where said NChannels is a member of a third group consisting of 8 to 16,
• where Knum is a member of a fourth group consisting of 2 to 4,
• where Bnum is a member of a fifth group consisting of 32 to 128,
• where Tclock is a member of the range of non-zero times from 0 nanoseconds(ns) to at most 2 ns;
• and
• B. each of said cores adapted to operate Nproc simultaneous and independent processes owning separate instructed resources of said PEM configured to locally implement part of Block LU Decomposition as a block processor of a block of Nblock rows and Nblock columns of numbers adapted to respond to channel receptions of at least one of said channels at said module communication interface,
• where Nblock is a member of a sixth group consisting of 16 to 32,
• where Nproc is a member of a seventh group consisting of 2 to 8.