Debugging translation block and debugging architecture
AssigneeIntel IP Corporation
InventorsBaraa Al-Dabagh, Dongsheng Bi, Roi Uziel
Life of this patent
Estimating the term…
Abstract
An electronic device includes one or more integrated circuits, a debugging translation block, and a bus connected to the one or more integrated circuits and the debugging translation block, the bus configured to provide a connection to one or more external devices, wherein the debugging translation block is configured to receive debugging commands from a testing host device via the bus, convert the debugging commands into debugging input data, and provide the debugging input data to a debugging state machine of a first integrated circuit of the one or more integrated circuits.
Claims20
An electronic device comprising:
- one or more integrated circuits;
- a debugging translation block;
- and
- a bus connected to the one or more integrated circuits and the debugging translation block, the bus configured to provide a connection to one or more external devices;
- wherein the debugging translation block is configured to receive debugging commands from a testing host device via the bus, convert the debugging commands into debugging input data, and provide the debugging input data to a debugging state machine of a first integrated circuit of the one or more integrated circuits,
- wherein the debugging input data comprises debugging test data and debugging instructions, and wherein the debugging translation block is configured to provide the debugging test data and the debugging instructions to the debugging state machine of the first integrated circuit by providing the debugging test data and debugging instructions over a plurality of debugging signal lines.
An electronic device comprising:
- a first integrated circuit and second integrated circuit;
- and
- a debugging translation block configured to receive debugging commands from a testing host device via a pipe connection provided by the first integrated circuit, convert the debugging commands into debugging input data, and to provide the debugging input data to a debugging state machine of the second integrated circuit,
- wherein the debugging input data comprises debugging test data and debugging instructions, and wherein the debugging translation block is configured to provide the debugging test data and the debugging instructions to the debugging state machine of the second integrated circuit by providing the debugging test data and debugging instructions over a plurality of debugging signal lines.
An electronic device comprising:
- a first integrated circuit and a second integrated circuit;
- a debugging translation block;
- and
- a bus connecting the first integrated circuit and the debugging translation block,
- wherein the first integrated circuit is configured to receive debugging commands from a testing host device and to provide the debugging commands to the debugging translation block over the bus,
- and the debugging translation block is configured to convert the debugging commands into debugging input data and to provide the debugging input data to a debugging state machine of the second integrated circuit,
- the electronic device further comprising a plurality of signal lines connecting the debugging translation block and the debugging state machine, wherein the debugging translation block is configured to provide the debugging input data to the debugging state machine on the plurality of signal lines.
A method for testing integrated circuits, the method comprising:
- receiving, at a debugging translation block, debugging commands from a testing host device via a bus that is connected to one or more integrated circuits and configured to provide a connection to one or more external devices;
- converting, at the debugging translation block, the debugging commands into debugging input data;
- and
- providing, from the debugging translation block, the debugging input data to a debugging state machine of a first integrated circuit of the one or more integrated circuits,
- wherein the debugging input data comprises debugging test data and debugging instructions, and wherein providing the debugging test data and the debugging instructions to the debugging state machine of the first integrated circuit comprises providing the debugging test data and debugging instructions over a plurality of debugging signal lines.
Dependencies are inferred from the claim text.