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US 10,474,467 B2Granted
Processor instruction sequence translation
AssigneeInternational Business Machines Corporation
InventorsGiles R. Frazier, Michael Karl Gschwind
Life of this patent
Estimating the term…
Abstract
Computer readable medium and apparatus for translating a sequence of instructions is disclosed herein. In one embodiment, an operation includes recognizing a candidate multi-instruction sequence, determining that the multi-instruction sequence corresponds to a single instruction, and executing the multi-instruction sequence by executing the single instruction.
Claims12
A system, comprising:
- a memory storing a block of program instructions;
- and
- a processor comprising a translator module configured to:
- fetch the block of program instructions and transfer the block of program instructions to a cache, wherein the block of program instructions spans a plurality of cache-lines in the cache;
- scanning the block of program instructions in the cache to determine whether the plurality of instructions contain a multi-instruction sequence that corresponds to a first instruction by shifting the block of program instructions through an instruction buffer to recognize that opcodes of the multi-instruction sequence appear in a specific order and are interdependent;
- determine whether the multi-instruction sequence is fully contained within a single line of the cache, wherein an intervening instruction that is not an instruction of the multi-instruction sequence is disposed between at least two instructions of the block of program instructions that constitute the multi-instruction sequence in the cache;
- responsive to determining that the multi-instruction sequence is fully contained within a single line of the cache,
- replace the multi-instruction sequence with the first instruction in the cache, and
- execute the multi-instruction sequence by executing the first instruction,
- responsive to determining that the multi-instruction sequence is fully contained within more than a single line of the cache,
- execute individual instructions of the multi-instruction sequence in the block of program instructions.
8 more elements
A computer readable storage medium having stored thereon instructions that when executed by a processor cause a processor to perform an operation for translating a sequence of instructions, comprising:
- fetching a block of program instructions and transferring the block of program instructions to a cache, wherein the block of program instructions spans a plurality of cache-lines in the cache;
- scanning the block of program instructions in the cache to determine whether the block of program instructions contain a multi-instruction sequence that corresponds to a first instruction by shifting the block of program instructions through an instruction buffer to recognize that opcodes of the multi-instruction sequence appear in a specific order and are interdependent;
- determining whether the multi-instruction sequence is fully contained within a single line of the cache, wherein an intervening instruction that is not an instruction of the multi-instruction sequence is disposed between at least two instructions of the block of program instructions that constitute the multi-instruction sequence in the cache;
- responsive to determining that the multi-instruction sequence is fully contained within a single line of the cache,
- replacing the multi-instruction sequence with the first instruction in the cache, and
- executing the multi-instruction sequence by executing the first instruction,
- responsive to determining that the multi-instruction sequence is fully contained within more than a single line of the cache,
- executing individual instructions of the multi-instruction sequence in the block of program instructions.
5 more elements
Dependencies are inferred from the claim text.