Deep vision processor

A processor comprising:

• a load and store unit configured to load and store image pixel data and stencil data;
• a register unit, implementing a banked register file comprising a plurality of registers included in respective banks of registers, the register unit configured to:
• load and store a subset of the image pixel data from the load and store unit;
• and
• concurrently provide access to image pixel values stored in a register file entry of the banked register file, wherein the subset of the image pixel data comprises the image pixel values stored in the register file entry,
• wherein the stencil data comprises a stencil associated with a stencil size, the stencil size being implemented via one or more smaller stencil sizes of a plurality of smaller stencil sizes, wherein the banked register file stores the subset of the image pixel data in a group of registers of the plurality of registers selected based on the one or more smaller stencil sizes;
• an interconnect unit in communication with the register unit, the interconnect unit configured to:
• provide the image pixel values stored in the register file entry;
• and
• provide corresponding stencil data to the image pixel values stored in the register file entry;
• and
• a plurality of arithmetic logic units (ALUs) in communication with the interconnect configured to concurrently perform one or more operations on the image pixel values stored in the register file entry and the corresponding stencil data to the image pixel value is stored in the register file entry from the interconnect unit.