Dynamic pipeline throttling using confidence-based weighting of in-flight branch instructions

An apparatus comprising:

• confidence fields configured to store confidence levels associated with in-flight branch instructions in an instruction pipeline;
• a branch instruction queue (BIQ) configured to set an initial confidence entry in the branch instruction queue (BIQ) for in-flight branch instructions;
• and
• a throttler comprising:
• confidence level blocks configured to determine numbers of the in-flight branch instructions associated with each of the confidence levels;
• associate a weight with each one of the numbers of in-flight branch instructions associated with each of the confidence levels, to form weighted numbers;
• a weighted sum block configured to determine a weighted sum corresponding to a sum of the weighted numbers based on the category of the in-flight branch instructions and the number of in-flight branch instructions in each category;
• and
• a comparator configured to compare the weighted sum with a threshold and provide a throttling signal to indicate that instructions are to be throttled in a pipeline stage of the instruction pipeline, based on the comparison.

An apparatus comprising:

• means for setting an initial confidence entry for in-flight branch instructions;
• means for storing confidence levels associated with each of the in-flight branch instructions in an instruction pipeline of a processor;
• means for determining numbers of in-flight branch instructions associated with each category of the confidence levels;
• determining a weighted sum corresponding to a sum of weighted numbers, wherein a weight is associated with each one of the numbers of in-flight branch instructions associated with each of the confidence levels, to form weighted numbers based on the category of the in-flight branch instructions and the number of in-flight branch instructions in each category;
• means for comparing the weighted sum with a threshold;
• and
• means for providing a throttling signal to indicate that instructions are to be throttled in a pipeline stage of the instruction pipeline based on the comparison.