Instruction-based synchronization of operations including at least one SIMD scatter operation
AssigneeQUALCOMM Incorporated
InventorsEric Mahurin, Lucian Codrescu
Life of this patent
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Abstract
A method of determining an execution order of memory operations performed by a processor includes executing at least one single-instruction, multiple-data (SIMD) scatter operation by the processor to store data to a memory. The method further includes executing one or more instructions by the processor to determine the execution order of a set of memory operations. The set of memory operations includes the at least one SIMD scatter operation.
Claims26
A method of determining an execution order of memory operations performed by a processor, the method comprising:
- in response to detecting a single-instruction, multiple-data (SIMD) scatter instruction, scheduling execution of a store-release instruction after the SIMD scatter instruction, wherein the store-release instruction is configured to synchronize access to a memory;
- executing the SIMD scatter instruction by the processor to initiate a scatter operation;
- and
- executing the store-release instruction by the processor, wherein the scatter operation is performed prior to completion of the execution of the store-release instruction.
An apparatus comprising:
- a scatter detector unit configured to issue a store-release instruction in response to detecting a single-instruction, multiple-data (SIMD) scatter instruction;
- and
- an execution unit configured to receive the store-release instruction from the scatter detector unit, the execution unit configured to execute the SIMD scatter instruction to initiate a scatter operation, to execute a memory access instruction to initiate a memory access operation, and to execute the store-release instruction, wherein the scatter operation is configured to be performed prior to completion of the store-release instruction.
A non-transitory computer-readable medium storing instructions executable to perform operations by a processor, the operations comprising:
- in response to detecting a single-instruction, multiple-data (SIMD) scatter instruction, scheduling execution of a store-release instruction after the SIMD instruction, the store-release instruction configured to synchronize access to a memory;
- executing the SIMD scatter instruction by the processor to initiate a scatter operation;
- and
- executing the store-release instruction by the processor, wherein the scatter operation is configured to be performed prior to completion of the store-release instruction.
An apparatus comprising:
- means for issuing a scatter store-release instruction in response to detecting a single-instruction, multiple-data (SIMD) scatter instruction;
- and
- means for receiving the scatter store-release instruction from the means for issuing and for executing the SIMD scatter instruction to initiate a scatter operation and executing the scatter store-release instruction, wherein the scatter operation is configured to be performed prior to completion of the scatter store-release instruction.
Dependencies are inferred from the claim text.