Instructions and logic to perform floating-point and integer operations for machine learning

A hardware accelerator comprising:

• a fetch unit to fetch a single instruction to perform a combined multiply and add operation on a set of operands;
• a decode unit to decode the single instruction into a decoded instruction;
• and
• a dynamically configurable compute unit to perform operations at a precision and data-type of the set of operands, wherein the dynamically configurable compute unit is to receive the decoded instruction and execute at least a portion of the decoded instruction, wherein to execute at least the portion of the decoded instruction includes to generate an output based on the combined multiply and add operation, to generate the output includes to quantize an intermediate value having a first precision to a second precision that is lower than the first precision, and to quantize the intermediate value includes to stochastically round a fractional portion of intermediate data.

A non-transitory machine-readable medium storing instructions to cause one or more processors of an electronic device to perform operations comprising:

• configuring a hardware accelerator to fetch and decode a single instruction to perform a combined multiply and add operation on a set of operands and issue the single instruction for execution by a dynamically configurable compute unit;
• configuring the dynamically configurable compute unit to perform operations at a precision and data-type of the set of operands;
• and
• executing at least a portion of the single instruction at the dynamically configurable compute unit to generate an output based on the combined multiply and add operation, wherein to generate the output includes quantizing an intermediate value having a first precision to a second precision that is lower than the first precision, the quantizing including stochastically rounding a fractional portion of intermediate data.

A data processing system comprising:

• a memory device;
• and
• a hardware accelerator coupled with the memory device, wherein the hardware accelerator includes:
• a fetch unit to fetch a single instruction to perform a combined multiply and add operation on a set of operands;
• a decode unit to decode the single instruction into a decoded instruction;
• and
• a dynamically configurable compute unit to perform operations at a precision and data-type of the set of operands, wherein the dynamically configurable compute unit is to receive the decoded instruction and execute at least a portion of the decoded instruction, wherein to execute at least the portion of the decoded instruction includes to generate an output based on the combined multiply and add operation, to generate the output includes to quantize an intermediate value having a first precision to a second precision that is lower than the first precision, and to quantize the intermediate value includes to stochastically round a fractional portion of intermediate data.