Machine perception and dense algorithm integrated circuit
Assigneequadric.io, Inc.
InventorsNigel Drego, Aman Sikka, Mrinalini Ravichandran, Ananth Durbha, Robert Daniel Firu, Veerbhan Kheterpal
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Abstract
A circuit that includes a plurality of array cores, each array core of the plurality of array cores comprising: a plurality of distinct data processing circuits; and a data queue register file; a plurality of border cores, each border core of the plurality of border cores comprising: at least a register file, wherein: [i] at least a subset of the plurality of border cores encompasses a periphery of a first subset of the plurality of array cores; and [ii] a combination of the plurality of array cores and the plurality of border cores define an integrated circuit array.
Claims17
An integrated circuit comprising:
- a plurality of processing cores, each processing core of the plurality of processing cores comprising:
- at least one processing circuit;
- and
- at least one memory circuit;
- a plurality of peripheral cores, each peripheral core of the plurality of peripheral cores comprising:
- at least one memory circuit,
- wherein:
- [i] at least a subset of the plurality of peripheral cores is arranged along a periphery of a first subset of the plurality of processing cores;
- and
- [ii] a combination of the plurality of processing cores and the plurality of peripheral cores define an integrated circuit array;
- a dispatch controller that provides data movement instructions, wherein the data movement instructions comprise a data flow schedule that:
- defines an automatic movement of data within the integrated circuit array;
- and
- sets one or more peripheral cores of the plurality of peripheral cores to a predetermined constant value if no data is provided to the one or more peripheral cores according to the predetermined data flow schedule.
An integrated circuit comprising:
- a plurality of processing cores, each processing core of the plurality of processing cores comprising:
- at least one multiply accumulator;
- and
- at least one memory circuit;
- a plurality of peripheral cores, each peripheral core of the plurality of peripheral cores comprising:
- at least one memory circuit,
- wherein:
- [i] at least a subset of the plurality of peripheral cores is arranged along a periphery of a first subset of the plurality of processing cores;
- and
- [ii] a combination of the plurality of processing cores and the plurality of peripheral cores define an integrated circuit array;
- a dispatch controller that provides data movement instructions, wherein the data movement instructions comprise a data flow schedule that:
- defines an automatic movement of data within the integrated circuit array;
- and
- sets one or more peripheral cores of the plurality of peripheral cores to a predetermined constant value if no data is provided to the one or more peripheral cores according to the predetermined data flow schedule.
Dependencies are inferred from the claim text.