Multi-rank SDRAM control method and SDRAM controller
AssigneeFanuc Corporation
InventorTakaaki Komatsu
Life of this patent
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Abstract
To provide a multi-rank SDRAM control method and an SDRAM controller that prevent performance degradation and minimize increase in parts count even in a multi-rank SDRAM configuration. A multi-rank SDRAM control method controls a multi-rank SDRAM formed by connecting data buses of multiple SDRAM devices. In each of the multiple SDRAM devices, only a data mask signal for a rank of the SDRAM device, which is to be accessed, is negated, whereby an access to the rank is executed.
Claims5
A multi-rank SDRAM control method of controlling a multi-rank SDRAM formed by connecting data ports of multiple SDRAM devices,
- wherein each of the ranks of the multi-rank SDRAM is directly connected to a same set of data lines for data input or data output as different ranks of the multi-rank SDRAM such that the data input or the data output is only performed for one of the ranks of the multi-rank SDRAM at a time, and
- wherein, in each of the multiple SDRAM devices, a chip select signal is common to all the ranks, data mask signals are separated for each rank, and only a data mask signal of the SDRAM device of a rank to be accessed is negated, whereby an access to the rank is executed.
A multi-rank SDRAM control method of controlling a multi-rank SDRAM formed by connecting data ports of multiple SDRAM devices,
- wherein each of the ranks of the multi-rank SDRAM is directly connected to a same set of data lines for data input or data output as different ranks of the multi-rank SDRAM such that the data input or the data output is only performed for one of the ranks of the multi-rank SDRAM at a time,
- wherein, in each of the multiple SDRAM devices, a chip select signal is common to all the ranks, data mask signals are separated for each rank, and only a data mask signal of the SDRAM device of a rank to be accessed is negated, whereby an access to the rank is executed,
- wherein the multi-rank SDRAM has as many ranks as any power of two, and the rank is selected using a low-order bit of an address of the multi-rank SDRAM, and
- wherein an address bit group in a place one bit higher than the low-order bit used for selecting the rank is used as a column address of the multiple SDRAM devices.
Dependencies are inferred from the claim text.