US 10,474,390 B1 · Systems and method for buffering data using a delayed write data signal and a memory receiving write addresses in a first order and read addresses in a second order

Abstract

A circuit includes a memory and an address generator configured to generate a write address signal and a read address signal, where the write address signal has a first delay relative to the read address signal. The memory is configured to receive a first plurality of write addresses, from the write address signal, including a first plurality of addresses of the memory in a first order, and write, to the first plurality of write addresses, a first plurality of data words during a first time period. The memory is further configured to receive a first plurality of read addresses, from the read address signal, including the first plurality of addresses in a second order, and read, from the first plurality of read addresses, the first plurality of data words during a second time period. The first and second time periods partially overlap. The first order may be one of a natural order and a modified order, with the second order being the other of the natural order and the modified order, and the modified order may be one of a bit-reversed order and a digit-reversed order. The memory may have different write modes, and may be a read-before-write memory or a write-before-read memory.

Claims20

Dependent claims

A circuit, comprising:

an address generator configured to generate a write address signal and a read address signal, wherein the write address signal has a first delay relative to the read address signal;
a write data delay circuit configured to generate a delayed write data signal using a write data signal based on the first delay;
and
a memory configured to:
receive, from the write address signal, a first plurality of write addresses including a first plurality of addresses of the memory in a first order;
write, to the first plurality of write addresses, a first plurality of data words of the delayed write data signal during a first time period;
receive, from the read address signal, a first plurality of read addresses including the first plurality of addresses of the memory in a second order;
and
read, from the first plurality of read addresses, the first plurality of data words during a second time period,
wherein the first delay is configured to eliminate an overlapping of read and write addresses during each of one or more clock cycles of a first overlap time period of the first and second time periods.

7 more elements

A method, comprising:

providing, to a memory, a write address signal and a read address signal, wherein the write address signal has a first delay relative to the read address signal;
generate a delayed write data signal using a write data signal based on the first delay;
writing, to the memory, a first plurality of data words of the delayed write data signal at a plurality of addresses according to a first order based on the write address signal during a first time period including a first clock cycle, wherein the writing of the first plurality of data words includes:
during the first clock cycle, writing a first data word of the first plurality of data words at a first address of the plurality of addresses;
and
reading, from the memory, the first plurality of data words at the plurality of addresses according to a second order based on the write address signal during a second time period including the first clock cycle, wherein the reading of the first plurality of data words includes:
during the first clock cycle, reading a second data word of the first plurality of data words at a second address of the plurality of addresses, wherein the second address is different from the first address.

4 more elements

Dependencies are inferred from the claim text.

Systems and method for buffering data using a delayed write data signal and a memory receiving write addresses in a first order and read addresses in a second order

Life of this patent

Systems and method for buffering data using a delayed write data signal and a memory receiving write addresses in a first order and read addresses in a second order

Life of this patent

Abstract

Claims20