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US 10,474,376 B2Granted
Memory controller, memory system including the same and operation method of memory controller
AssigneeSK hynix Inc.
InventorsJing-Zhe Xu, Jung-Hyun Kwon, Sung-Eun Lee, Jae-Sun Lee, Sang-Gu Jo
Life of this patent
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Abstract
An operating method of a memory controller may include determining a physical page to be accessed in a plurality of memory devices by mapping a logical address to a physical address; and determining a distribution pattern in which data of the physical page are distributed to the plurality of memory devices using the logical address.
Claims19
An operating method of a memory controller, comprising:
- determining a physical page to be accessed in a plurality of memory devices by mapping a logical address to a physical address;
- and
- determining a distribution pattern in which multiple units of data of the physical page are distributed to the plurality of memory devices using the logical address, each of the multiple units of data having a different data changing rate and at least two of the multiple units of data having a high data changing rate relative to remaining units of data of the multiple units of data;
- wherein each of the multiple units of data is one of a first type of data and a second type of data,
- wherein the distribution pattern identifies, for each unit of data, its type and the memory device, among the plurality of memory devices, in which it is stored, and
- wherein the distribution pattern is periodically changed using address mapping information to maintain uniform distribution of the at least two data units having a high data changing rate among the plurality of memory devices.
3 more elements
A memory system comprising:
- a plurality of memory devices suitable for being accessed by a physical address;
- and
- a memory controller suitable for controlling the memory devices,
- wherein the memory controller comprises:
- an address mapping circuit suitable for mapping a logical address to the physical address;
- and
- a data distribution circuit suitable for determining a distribution pattern in which multiple units of data of a physical page to be accessed in the plurality of memory devices using the physical address are distributed to the plurality of memory devices using the logical address, each of the multiple units of data having a different data changing rate and at least two of the multiple units of data having a high data changing rate relative to remaining units of data of the multiple units of data;
- wherein each of the multiple units of data is one of a first type of data and a second type of data,
- wherein the distribution pattern identifies, for each unit of data, its type and the memory device, among the plurality of memory devices, in which it is stored, and
- wherein the distribution pattern is periodically changed using address mapping information to maintain uniform distribution of the at least two data units having a high data changing rate among the plurality of memory devices.
7 more elements
A memory controller controlling a plurality of memory devices accessed by a physical address, the memory controller comprising:
- an address mapping circuit suitable for mapping a logical address to the physical address;
- and
- a data distribution circuit suitable for determining a distribution pattern in which multiple units of data of a physical page to be accessed in the plurality of memory devices using the physical address are distributed to the plurality of memory devices using the logical address, each of the multiple units of data having a different data changing rate and at least two of the multiple units of data having a high data changing rate relative to remaining units of data of the multiple units of data;
- wherein each of the multiple units of data is one of a first type of data and a second type of data,
- wherein the distribution pattern identifies, for each unit of data, its type and the memory device, among the plurality of memory devices, in which it is stored, and
- wherein the distribution pattern is periodically changed using address mapping information to maintain uniform distribution of the at least two data units having a high data changing rate among the plurality of memory devices.
3 more elements
Dependencies are inferred from the claim text.