Runtime address disambiguation in acceleration hardware

A memory ordering circuit comprising:

• a memory interface coupled to a memory, the memory to store data corresponding to instructions being executed for a program;
• an operations queue coupled to the memory interface, the operations queue to buffer memory operations corresponding to the instructions;
• a set of input queues coupled to the memory interface and to acceleration hardware, which is to execute a sub-program corresponding to the instructions, the set of input queues comprising:
• a store address queue to receive, from the acceleration hardware, a first address of the memory for a store operation of the memory operations, and
• a store data queue to receive, from the acceleration hardware, first data to be stored at the first address in completion of the store operation;
• a disambiguator circuit coupled to the set of input queues and to the acceleration hardware, the disambiguator circuit including a disambiguator queue, wherein each of the memory operations comprises an indicator field that when set to a first value causes a respective query of the disambiguator circuit and when set to a second value does not cause the respective query of the disambiguator circuit;
• and
• an operations manager circuit coupled to the set of input queues and the disambiguator circuit, the operations manager circuit to:
• schedule the store operation, which resides in the operations queue, to issue to the memory upon receipt of the first address;
• and
• store an entry in the disambiguator queue, the entry comprising the first address and a pointer into the store data queue to a location at which to receive the first data for the store operation, wherein locations within the store data queue correspond to out-of-order receipt of data from the acceleration hardware.

A method comprising:

• queuing memory operations in an operations queue of a memory ordering circuit, the memory operations directed towards a memory and in association with acceleration hardware, wherein the queuing includes queuing a load operation of the memory operations in the operations queue and the load operation comprises an indicator field that when set to a first value causes a query of a disambiguator circuit and when set to a second value does not cause the query of the disambiguator circuit;
• receiving, into a load address queue of a set of input queues, a load address received from the acceleration hardware for the load operation;
• determining, by the disambiguator circuit coupled to the memory ordering circuit, when the indicator field of the load operation is set to the first value, the load address matches a store address buffered in a store address queue for a store operation of the memory operations, the store operation semantically preceding the load operation according to program order;
• and
• marking, by the memory ordering circuit to schedule completion of the load operation and in response to the determining, the load operation as a store forward with a pointer to a location, within a store data queue of the set of input queues, for reception of data to complete the store operation and the load operation.