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US 10,474,360 B2Granted
Memory system with selective access to first and second memories
AssigneeToshiba Memory Corporation
InventorYasushi Nagadomi
Life of this patent
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Abstract
A memory system includes a nonvolatile memory having a plurality of nonvolatile memory chips incorporated therein, a control circuit that controls the nonvolatile memory, an MPU that controls the control circuit, and an interface circuit that communicates with a host, all of which are mounted on a board of the memory system, and the memory system further includes a bus switch that switches connection of a signal line between the control circuit and the nonvolatile memory chips.
Claims7
A memory package comprising:
- a first plurality of memory chips;
- a first interface configured to receive an IO signal, the IO signal including an access address;
- a second interface configured to receive a first selection signal, the first selection signal selecting a first target memory chip and not including an access address;
- and
- a third interface configured to receive a second selection signal different from the first selection signal, the second selection signal selecting a second target memory chip and not including an access address;
- wherein
- in a case that a memory chip among the first plurality of memory chips is in a first state, the memory chip is enabled to receive the IO signal,
- in a case that the memory chip is not in the first state, the memory chip is not enabled to receive the IO signal, and
- the first state is a state of being selected as both the first target memory chip and the second target memory chip, wherein
- the first selection signal selects a second plurality of memory chips among the first plurality of memory chips, and
- each memory chip among the second plurality of memory chips corresponds to the first target memory chip.
8 more elements
A memory package comprising:
- a first plurality of memory chips;
- a first interface configured to receive an IO signal, the IO signal including an access address, and having a first output connected to a first group of the first plurality of memory chips and a second output connected to a second group of the first plurality of memory chips;
- a second interface connected to the first group and configured to receive a first selection signal, the first selection signal selecting a first target memory chip and not including an access address;
- and
- a third interface connected to the second group and configured to receive a second section signal different from the first selection signal, the second selection signal selecting a second target memory chip and not including an access address.
2 more elements
Dependencies are inferred from the claim text.