Enabling system low power state when compute elements are active

A method comprising:

• causing a fabric and a memory controller to enter a low power consumption state at least partially in response to a determination that the fabric and the memory controller are idle and while a compute element, coupled to the fabric and the memory controller, is in an active state,
• wherein the memory controller and the fabric are shared amongst a plurality of components of a System on Chip (SOC) device, wherein the plurality of components of the SOC comprise the fabric, the memory controller, and the compute element, wherein the compute element is prevented from accessing the shared fabric and the shared memory controller in response to a determination that the fabric and the memory controller have entered the low power consumption state.

A non-transitory computer-readable medium comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to:

• cause a fabric and a memory controller to enter a low power consumption state at least partially in response to a determination that the fabric and the memory controller are idle and while a compute element, coupled to the fabric and the memory controller, is in an active state,
• wherein the memory controller and the fabric are to be shared amongst a plurality of components of a System on Chip (SOC) device, wherein the plurality of components of the SOC comprise the fabric, the memory controller, and the compute element, wherein the compute element is to be prevented from accessing the shared fabric and the shared memory controller in response to a determination that the fabric and the memory controller have entered the low power consumption state.

A computing system comprising:

• memory to store data to be accessed by one or more processor cores of on an SOC integrated circuit device, wherein the memory is external to the SOC integrated circuit device;
• the SOC integrated circuit device to comprise a fabric, a memory controller, coupled to the memory, and logic, at least a portion of which is in hardware, to cause the fabric and the memory controller to enter a low power consumption state at least partially in response to a determination that the fabric and the memory controller are idle and while one or more of the one or more processor cores are in an active state,
• wherein the memory controller and the fabric are to be shared amongst a plurality of components of a System on Chip (SOC) device, wherein the plurality of components of the SOC comprise the fabric, the memory controller, and the compute element, wherein the compute element is to be prevented from accessing the shared fabric and the shared memory controller in response to a determination that the fabric and the memory controller have entered the low power consumption state.