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US 10,474,218 B2Granted
Dynamically controlling cache size to maximize energy efficiency
AssigneeIntel Corporation
InventorsAvinash N. Ananthakrishnan, Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Nadav Shulman, Alon Naveh, Hisham Abu-Salah
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Abstract
In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.
Claims25
A processor comprising:
- a plurality of cores, wherein each of the plurality of cores includes a plurality of caches;
- a shared cache coupled to the plurality of cores, wherein the shared cache is to be shared by the plurality of cores, and wherein the shared cache includes a plurality of portions that each include at least one way;
- and
- a power control circuitry coupled to the plurality of cores and to the shared cache, the power control circuitry to:
- determine a number of cache hits, and a number of cache misses, to the shared cache from the plurality of cores;
- provide control for a dynamically variable size of the shared cache available for use by the plurality of cores, through at least one of the plurality of portions being enabled or disabled, based at least in part on the determined numbers of cache hits and cache misses;
- and
- provide control for at least one of the plurality of portions of the shared cache being maintained in a retention state, when the plurality of cores are to be in a low power state, and while at least another of the plurality of portions of the shared cache is to be in a lower power state than the retention state, wherein in the retention state data stored in the at least one of the plurality of portions, which is being maintained in the retention state, is to be retained.
5 more elements
An apparatus comprising:
- a plurality of cores, wherein each of the plurality of cores includes a plurality of caches;
- a shared cache coupled to the plurality of cores, wherein the shared cache is to be shared by the plurality of cores, and wherein the shared cache includes a plurality of portions that each include at least one way;
- circuitry to determine a number of cache hits, and a number of cache misses, to the shared cache from the plurality of cores;
- circuitry to provide control for a dynamically variable size of the shared cache available for use by the plurality of cores, through at least one of the plurality of portions being enabled or disabled, based at least in part on the determined numbers of cache hits and cache misses;
- and
- circuitry to provide control for at least one of the plurality of portions of the shared cache being maintained in a retention state, when the plurality of cores are to be in a low power state, and while at least another of the plurality of portions of the shared cache is to be in a lower power state than the retention state, wherein in the retention state data stored in the at least one of the plurality of portions, which is being maintained in the retention state, is to be retained.
3 more elements
A method comprising:
- storing data in a plurality of caches of each of a plurality of cores;
- sharing a shared cache among the plurality of cores, wherein the shared cache includes a plurality of portions that each include at least one way;
- determining a number of cache hits, and a number of cache misses, to the shared cache from the plurality of cores;
- providing control for a dynamically variable size of the shared cache available for use by the plurality of cores, through at least one of the plurality of portions being enabled or disabled, based at least in part on the determined numbers of cache hits and cache misses;
- and
- providing control for at least one of the plurality of portions of the shared cache being maintained in a retention state, when the plurality of cores are in a low power state, and while at least another of the plurality of portions of the shared cache is in a lower power state than the retention state, wherein in the retention state data stored in the at least one of the plurality of portions, which is being maintained in the retention state, is retained.
3 more elements
Dependencies are inferred from the claim text.