Control apparatus, control method of control apparatus, and storage medium

A method of controlling an apparatus having a processor, a DRAM (Dynamic Random Access Memory), a reset control circuit that resets the processor, and a power control circuit that controls supply of power to the processor, and which is able to shift into a power-saving mode, the method comprising:

• a first fetching step, by the processor, to fetch from the DRAM a reset instruction for causing the reset control circuit to perform reset of the processor;
• a first giving step to give an instruction to cause the reset control circuit to reset the processor in accordance with the reset instruction fetched from the DRAM;
• a second fetching step, by the processor, to fetch from the DRAM a power control instruction for causing the power control circuit to stop supply of power to the processor;
• and
• a second giving step to give an instruction to cause the power control circuit to stop supply of power to the processor in accordance with the power control instruction fetched from the DRAM, wherein,
• after a predetermined condition to shift a power mode of the apparatus into the power saving mode is satisfied before supply of power to the processor is stopped, performing a memory control step to cause the DRAM to perform a self-refresh operation, then the first fetching step, the first giving step, the second fetching step, and the second giving step are performed.

A non-transitory computer-readable medium storing a program for causing a computer to perform a method of controlling an apparatus having a processor, a DRAM (Dynamic Random Access Memory), a reset control circuit that resets the processor, and a power control circuit that controls supply of power to the processor, and which is able to shift into a power-saving mode, the method comprising:

• a first fetching step, by the processor, to fetch from the DRAM a reset instruction for causing the reset control circuit to perform reset of the processor;
• a first giving step to give an instruction to cause the reset control circuit to reset the processor in accordance with the reset instruction fetched from the DRAM;
• a second fetching step, by the processor, to fetch from the DRAM a power control instruction for causing the power control circuit to stop supply of power to the processor;
• and
• a second giving step to give an instruction to cause the power control circuit to stop supply of power to the processor in accordance with the power control instruction fetched from the DRAM, wherein,
• after a predetermined condition to shift a power mode of the apparatus into the power saving mode is satisfied before supply of power to the processor is stopped, performing a memory control step to cause the DRAM to perform a self-refresh operation, then the first fetching step, the first giving step, the second fetching step, and the second giving step are performed.