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US 10,474,133 B2Granted
Inspection device for inspecting wafer and method of inspecting wafer using the same
AssigneeSamsung Electronics Co., Ltd.
InventorsJanghee Lee, Yoo Jin Jeong, Sangbong Park, Byeonghwan Jeon
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Abstract
An inspection device includes a first processor, a second processor, and a server. The first processor detects first coordinates of first feature points from first images in a first image set. The second processor detects second coordinates of second feature points from second images in a second image set. The server generates reference coordinates based on the first coordinates and the second coordinates. The reference coordinates are transmitted to the first processor and the second processor. The first and second image sets correspond to scanned swaths on a wafer.
Claims20
An inspection device, comprising:
- a first processor to detect first coordinates of first feature points from first images in a first image set, the first coordinates of the first feature points including 1-st to n-th first coordinates, where n is a natural greater than one;
- a second processor to detect second coordinates of second feature points from second images in a second image set, the second coordinates of the second feature points including 1-st to n-th second coordinates;
- and
- a server to generate 1-st to n-th reference coordinates based on the 1-st to n-th first coordinates and the 1-st to n-th second coordinates, respectively, and to transmit the 1-st to n-th reference coordinates to the first processor and the second processor, wherein the first and second image sets correspond to a same scanned swath on a wafer, wherein:
- the 1-st reference coordinate is generated using the 1-st first coordinate and the 1-st second coordinate, and
- the n-th reference coordinate is generated using the n-th first coordinate and the n-th second coordinate.
3 more elements
An inspection method, comprising:
- receiving, from an image sensor, a plurality of image sets generated by scanning one inspection swath of a plurality of inspection swaths on a test wafer;
- detecting, by a first processor, first coordinates of first feature points from first images in a first image set among the plurality of image sets, the first coordinates of the first feature points including 1-st to n-th first coordinates, where n is a natural number greater than one;
- detecting, by a second processor, second coordinates of second feature points from second images in a second image set among the plurality of image sets, the second coordinates of the second feature points including 1-st to n-th second coordinates;
- generating, by a server, 1-st to n-th reference coordinates based on the 1-st to n-th first coordinates and the 1-st to n-th second coordinates, respectively;
- generating, by the first processor, first aligned images by aligning locations of the 1-st to n-th first coordinates to correspond to the 1-st to n-th reference coordinates;
- and
- generating, by the second processor, second aligned images by aligning locations of the 1-st to n-th second coordinates to correspond to the 1-st to n-th reference coordinates, wherein:
- the 1-st reference coordinate is generated using the 1-st first coordinate and the 1-st second coordinate, and
- the n-th reference coordinate is generated using the n-th first coordinate and the n-th second coordinate.
6 more elements
An apparatus, comprising:
- first logic circuit to detect first coordinates of first feature points from first images the first coordinates of the first feature points including 1-st to n-th first coordinates, where n is a natural number greater than one;
- second logic circuit to detect second coordinates of second feature points from second images, the first and second images corresponding to a same scanned swath on a wafer, the second coordinates of the second feature points including 1-st to n-th second coordinates;
- third logic circuit to generate 1-st to n-th reference coordinates based on the 1-st to n-th first and second coordinates of the first and second feature points of the first and second images, respectively;
- and
- fourth logic circuit to detect a defect of the wafer by comparing aligned first and second images based on the reference coordinates, wherein:
- the 1-st reference coordinate is generated using the 1-st first coordinate and the 1-st second coordinate, and
- the n-th reference coordinate is generated using the n-th first coordinate and the n-th second coordinate.
4 more elements
Dependencies are inferred from the claim text.