Adaptive time-to-digital converter and method

A method configured to control a time-to-digital converter (TDC) circuitry that includes a chain of n delay elements and a set of n sampling elements, each associated with a respective delay element, wherein the TDC is configured to determine a phase difference between a reference signal and a digitally controlled oscillator (DCO) signal, the method comprising:

• determining a gating enable signal based on an incremental delay for each delay element and a period of a phase locked loop (PLL) feedback signal;
• and
• providing the gating enable signal to gate circuitry that gates the PLL feedback signal, such that when the gating enable signal has an enable value the PLL feedback signal is provided to the n sampling elements and when the gating enable signal does not have the enable value a constant value is provided to the n sampling elements.

A method configured to control a time-to-digital converter (TDC) circuitry that includes a chain of n delay elements and a set of n sampling elements, each associated with a respective delay element, wherein the TDC is configured to determine a phase difference between a reference signal and a digitally controlled oscillator (DCO) signal, the method comprising:

• determining a desired incremental delay for the delay elements, wherein an incremental delay for a delay element corresponds to an amount of time that elapses between a time at which the reference signal is input to the delay element and a time at which the delay element outputs a respective clock signal;
• and
• controlling a supply voltage for the delay elements to cause the delay elements to exhibit the desired incremental delay.