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US 10,473,718 B2Granted
Multibit vectored sequential with scan
AssigneeIntel Corporation
InventorsAmit Agarwal, Ram Krishnamurthy, Satish Damaraju, Steven Hsu, Simeon Realov
Life of this patent
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Abstract
An apparatus is provided which comprises: a multi-bit quad latch with an internally coupled level sensitive scan circuitry; and a combinational logic coupled to an output of the multi-bit quad latch. Another apparatus is provided which comprises: a plurality of sequential logic circuitries; and a clocking circuitry comprising inverters, wherein the clocking circuitry is shared by the plurality of sequential logic circuitries.
Claims22
An apparatus comprising:
- a multi-bit sequential including a first sequential circuitry and a second sequential circuitry;
- and
- a multi-bit scan circuitry to provide scan of data associated with the multi-bit sequential, wherein the multi-bit scan circuitry comprises a first bit-cell and a second bit-cell, wherein part of the first bit-cell of the multi-bit scan circuitry is coupled in a feedback path of the first sequential circuitry, and wherein part of the second bit-cell of the multi-bit scan circuitry is coupled in a feedback path of the second sequential circuitry.
An apparatus comprising:
- a multi-bit quad latch with an internally coupled level-sensitive scan circuitry;
- and
- a combinational logic coupled to an output of the multi-bit quad latch.
A system comprising:
- a memory;
- a processor coupled to the memory, the processor including:
- a multi-bit quad latch with an internally coupled level-sensitive scan circuitry;
- and
- a combinational logic coupled to an output of the multi-bit quad latch;
- and
- a wireless interface to allow the processor to communicate with another device.
4 more elements
Dependencies are inferred from the claim text.