Data packing techniques for hard-wired multiplier circuits

An apparatus comprising:

• a hard-wired integer multiplier circuit configured to multiply a first physical operand and a second physical operand;
• and
• a processor configured to:
• map a first logical operand to a first portion of the first physical operand;
• map a second logical operand to a second portion of the first physical operand;
• insert zero padding bits between the first portion of the first physical operand and the second portion of the first physical operand;
• map a third logical operand to the second physical operand;
• and
• multiply the first physical operand and the second physical operand using the hard-wired integer multiplier circuit to provide a multiplication result that includes a first portion comprising a product of the first logical operand and the third logical operand, and a second portion comprising a product of the second logical operand and the third logical operand.

One or more computer storage media comprising computer-executable instructions directed to:

• mapping a first logical operand to a first portion of a first physical operand;
• mapping a second logical operand to a second portion of the first physical operand;
• inserting zero padding bits between the first portion of the first physical operand and the second portion of the first physical operand;
• and
• mapping a third logical operand to a second physical operand;
• and
• multiplying the first physical operand and the second physical operand using a hard-wired integer multiplier circuit to provide a multiplication result that includes a first portion comprising a product of the first logical operand and the third logical operand, and a second portion comprising a product of the second logical operand and the third logical operand;
• wherein the hard-wired integer multiplier circuit is configured to multiply the first physical operand and the second physical operand.