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US 10,467,180 B2Granted
Slave device for a serial synchronous full duplex bus system
AssigneeInfineon Technologies AG
InventorsAlbert Missoni, Matthias Pichler
Life of this patent
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Abstract
A slave device for a serial synchronous full duplex bus system, which has a data input stage, a clock input stage, an interface logic, a synchronization delay flip-flop, and a data output stage. The slave device is manufactured using nanometer technologies. Also, a method for operating the slave device.
Claims14
A slave device for a serial synchronous full duplex bus system, the slave device comprising:
- a data input stage configured to receive a medium voltage data bus signal from a master device of the bus system and configured to provide a medium voltage data signal, wherein the medium voltage data signal is supplied to a data signal level down shifter configured to produce a low voltage data signal corresponding to the medium voltage data signal;
- a clock input stage configured to receive a medium voltage clock bus signal from the master device of the bus system and configured to provide a medium voltage clock signal, wherein the medium voltage clock signal is supplied to a clock signal level down shifter configured to produce a low voltage clock signal corresponding to the medium voltage clock signal;
- an interface logic configured to receive the low voltage data signal and the low voltage clock signal and to carry out one or more logical operations in order to produce one or more low voltage output data signals based on the low voltage data signal and based on the low voltage clock signal;
- a synchronization delay flip-flop having a delay flip-flop data input, a delay flip-flop clock input, and a delay flip-flop data output,
- wherein an asynchronous medium voltage output data signal, which is based on the one or more low voltage output data signals, is supplied to the delay flip-flop data input, the asynchronous medium voltage output data signal being different than the medium voltage data signal,
- wherein a medium voltage output clock signal derived from the medium voltage clock bus signal in a medium voltage portion of the slave device is supplied to the delay flip-flop clock input, and
- wherein the delay flip-flop data output provides a synchronous medium voltage output data signal;
- and
- a data output stage configured to transmit a medium voltage data bus signal to the master device of the bus system,
- wherein the synchronous medium voltage output signal is supplied to the data output stage.
7 more elements
A method for operating a slave device for a serial synchronous full duplex bus system, the method comprising:
- receiving a medium voltage data bus signal from a master device of the bus system and providing a medium voltage data signal using a data input stage, wherein the medium voltage data signal is supplied to a data signal level down shifter configured to produce a low voltage data signal corresponding to the medium voltage data signal;
- receiving a medium voltage clock bus signal from the master device of the bus system and providing a medium voltage clock signal using a clock input stage, wherein the medium voltage clock signal is supplied to a clock signal level down shifter configured to produce a low voltage clock signal corresponding to the medium voltage clock signal;
- receiving the low voltage data signal and the low voltage clock signal and carrying out one or more logical operations using an interface logic in order to produce one or more low voltage output data signals based on the low voltage data signal and based on the low voltage clock signal;
- using a synchronization delay flip-flop having a delay flip-flop data input, a delay flip-flop clock input and a delay flip-flop data output,
- wherein an asynchronous medium voltage output data signal, which is based on the one or more low voltage output data signals, is supplied to the delay flip-flop data input, the asynchronous medium voltage output data signal being different than the medium voltage data signal,
- based on the one or more low voltage output data signals, is supplied to the delay flip-flop data input,
- wherein a medium voltage output clock signal derived from the medium voltage clock bus signal in a medium voltage portion of the slave device is supplied to the delay flip-flop clock input, and
- wherein the delay flip-flop data output provides a synchronous medium voltage output data signal;
- and
- transmitting a medium voltage data bus signal to the master device of the bus system using a data output stage, wherein the synchronous medium voltage output signal is supplied to the data output stage.
7 more elements
Dependencies are inferred from the claim text.