Video processing device
AssigneeFujitsu Ten Limited
InventorsYasuhiro Fukuda, Yoshihiro Shimano
Life of this patent
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Abstract
Provided is a video processing device that generates a display video signal to be supplied to a liquid crystal display having a liquid crystal that is driven by a frame inversion scheme and includes a control microcomputer and a video signal processor. The control microcomputer controls a data enable signal such that a display invalid section having a predetermined number of fields is set for an interlace video signal at a predetermined period based on a vertical synchronization signal included in the interlace video signal input from outside. The video signal processor generates the display video signal by setting the display invalid section for the interlace video signal based on the data enable signal and outputs the display video signal to the liquid crystal display.
Claims15
A video processing device that generates a display video signal to be supplied to a liquid crystal display having a liquid crystal that is driven by a frame inversion scheme, the video processing device comprising:
- a control microcomputer that controls a data enable signal of an interlace video signal that is input to the control microcomputer from outside the control microcomputer, the interlace video signal input to the control microcomputer having a series of fields each of which includes a data signal and a vertical synchronization signal, the control microcomputer controlling the data enable signal such that a display invalid section having a length corresponding to a predetermined number of the fields is set for the interlace video signal at a predetermined period based on the vertical synchronization signal to cause skipping of a video output for one field at the predetermined period to inverse a polarity of an electrode of the liquid crystal display;
- and
- a video signal processor that generates the display video signal by setting the display invalid section for the interlace video signal based on the data enable signal controlled by the control microcomputer and outputs the display video signal to the liquid crystal display.
A video display system that displays a video, the video display system comprising:
- a liquid crystal display having a liquid crystal that is driven by a frame inversion scheme;
- and
- a video processing device that generates a display video signal to be supplied to the liquid crystal display,
- wherein the video processing device includes
- a control microcomputer that controls a data enable signal of an interlace video signal that is input to the control microcomputer from outside the control microcomputer, the interlace video signal input to the control microcomputer having a series of fields each of which includes a data signal and a vertical synchronization signal, the control microcomputer controlling the data enable signal such that a display invalid section having a length corresponding to a predetermined number of the fields is set for the interlace video signal at a predetermined period based on the vertical synchronization signal to cause skipping of a video output for one field at the predetermined period to inverse a polarity of an electrode of the liquid crystal display;
- a video signal processor that generates the display video signal by setting the display invalid section for the interlace video signal based on the data enable signal controlled by the control microcomputer and outputs the display video signal to the liquid crystal display.
A video processing method of generating a display video signal to be supplied to a liquid crystal display having a liquid crystal that is driven by a frame inversion scheme, the method comprising the steps of:
- (a) controlling a data enable signal of an interlace video signal that is input from outside, the interlace video signal having a series of fields each of which includes a data signal and a vertical synchronization signal, the data enable signal being controlled such that a display invalid section having a length corresponding to a predetermined number of the fields is set for the interlace video signal at a predetermined period based on the vertical synchronization signal to cause skipping of a video output for one field at the predetermined period to inverse a polarity of an electrode of the liquid crystal display;
- (b) generating the display video signal by setting the display invalid section for the interlace video signal based on the data enable signal that has been controlled and outputting the display video signal to the liquid crystal display.
Dependencies are inferred from the claim text.