Valid lane training

An apparatus comprising:

• physical layer logic to:
• send one or more link training signals comprising instances of a link training pattern on a plurality of lanes of a physical link, wherein the plurality of lanes comprise at least one valid lane and a plurality of data lanes;
• enter an active link state based on training of the plurality of lanes using the link training signals;
• send a valid signal on the valid lane during the active link state, wherein the valid signal comprises a signal held at a value for a defined first duration and indicates that data is to be sent on the plurality of data lanes in a second defined duration subsequent to the first duration;
• and
• send the data, during the active link state, on the plurality of data lanes during the second defined duration.

A system comprising:

• an interconnect comprising a plurality of lanes, wherein the plurality of lanes include a plurality of dedicated data lanes and at least one dedicated valid signal lane;
• a first device;
• and
• a second device communicatively coupled to the first device using the interconnect, wherein the second device is to:
• send one or more link training signals comprising instances of a link training pattern to the first device on the plurality of lanes;
• enter an active link state based on training of the plurality of lanes using the link training signals;
• send a valid signal to the first device on the valid lane during the active link state, wherein the valid signal comprises a signal held at a value throughout a first signaling window and indicates that data is to be sent on the plurality of data lanes in a second signaling window subsequent to the first signaling window;
• and
• send the data, during the active link state, to the first device on the plurality of data lanes during the second signaling window.