# US 10,455,708 B2 · Multilayered substrate and method for manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,455,708 B2 - Document ID: US10455708B2 - Status: Granted - Kind: B2 - Application number: 15/810,343 - Filed: 2017-11-13 - Published: 2018-03-08 - Granted: 2019-10-22 - Earliest claimed: 2015-06-29 - Assignees: Samsung Electro-Mechanics Co., Ltd. - Applicants: Samsung Electro-Mechanics Co., Ltd. - Inventors: Seok-Hwan Ahn; Mi-Sun Hwang; Young-Gwan Ko; Jong-Seok Bae; Myung-Sam Kang - Web page: https://patentgrep.com/patent/US10455708B2 ## CPC - H05K 3/4644: {by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602)} - H05K 1/0271: {Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion} - H05K 1/09: Use of materials for the {conductive, e.g. } metallic pattern - H05K 1/113: {Via provided in pad; Pad over filled via} - H05K 1/115: {Via connections; Lands around holes or via connections (H05K1/112 takes precedence)} - H05K 1/165: {incorporating printed inductors} - H05K 3/007: {Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier (H05K1/187, H05K3/20 and H05K3/4682 take precedence)} - H05K 3/06: the conductive material being removed chemically or electrolytically, e.g. by photo-etch process {(semi-additive methods H05K3/108)} - H05K 3/4617: {characterized by laminating only or mainly similar single-sided circuit boards} - H05K 3/4682: {Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil} - H05K 3/4688: {Composite multilayer circuits, i.e. comprising insulating layers having different properties (having a special base or central core H05K3/4602)} - H05K 2201/09136: Means for correcting warpage - H05K 2201/09454: Inner lands, i.e. lands around via or plated through-hole in internal layer of multilayer PCB - H05K 2201/09509: Blind vias, i.e. vias having one side closed - H05K 2201/09563: Metal filled via - H05K 2201/096: Vertically aligned vias, holes or stacked vias - H05K 2201/09827: Tapered, e.g. tapered hole, via or groove - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ## Abstract A multilayered substrate in accordance with an aspect of the present disclosure may include an insulating layer, a conductive pattern embedded, at least partially, in the insulating layer, and a bump being electrically connected to the conductive pattern and penetrating the insulating layer. The bump may include a low melting point metal layer having a melting point lower than a melting point of the conductive pattern and a high melting point metal layer having a melting point higher than the melting point of the low melting point metal layer and having a latitudinal cross-sectional area smaller than a latitudinal cross-sectional area of the low melting point metal layer. ## Claims ### Claim 1 A multilayered substrate, comprising: an insulating layer; a conductive pattern embedded, at least partially, in the insulating layer; a metal pattern formed in a protruding manner on the outermost surface of the insulating layer; and a bump being electrically connected to the conductive pattern and penetrating the insulating layer, wherein the bump comprises: a low melting point metal layer having a melting point lower than a melting point of the conductive pattern; and a high melting point metal layer having a melting point higher than the melting point of the low melting point metal layer and having a latitudinal cross-sectional area smaller than a latitudinal cross-sectional area of the low melting point metal layer, wherein the high melting point metal layer is interposed within the insulating layer between the at least partially embedded conductive pattern and the low melting point metal layer, wherein an interface between the high melting point layer and the embedded conductive pattern is formed within the insulating layer, and wherein the metal pattern is directly coupled with the low melting point metal layer. ### Claim 2 (depends on 1) The multilayered substrate of claim 1, wherein the insulating layer comprises photo-curable resin. ### Claim 3 (depends on 1) The multilayered substrate of claim 1, wherein the high melting point metal layer is made of copper. ### Claim 4 (depends on 1) The multilayered substrate of claim 1, wherein the insulating layer, the conductive pattern and the bump are each formed in plurality, and wherein the plurality of bumps penetrate the plurality of insulating layers, respectively, to provide interlayer connection between the plurality of conductive patterns. ### Claim 5 (depends on 4) The multilayered substrate of claim 4, wherein at least one of the plurality of conductive patterns is constituted with a plurality of conductive layers, each of which is made of a conductive material different from each other. ### Claim 6 (depends on 4) The multilayered substrate of claim 4, further comprising: a first metal pattern formed above an uppermost insulating layer of the plurality of insulating layers; a first insulating material laminated below a lowermost insulating layer of the plurality of insulating layers; a second metal pattern formed on a lower surface of the first insulating material; and a via penetrating the first insulating material so as to connect the second metal pattern with the conductive pattern embedded in one surface of the lowermost insulating layer. ### Claim 7 (depends on 6) The multilayered substrate of claim 6, wherein the first insulating material comprises photo-curable resin, and wherein the via is made of a material identical with a material of the bump. ### Claim 8 (depends on 6) The multilayered substrate of claim 6, further comprising: a second insulating material formed on the uppermost insulating layer so as to cover the first metal pattern; and a third metal pattern formed on the second insulating material. ### Claim 9 (depends on 1) The multilayered substrate of claim 1, wherein an upper surface of the high melting point metal layer is covered by a surface of the low melting point metal layer, and a lower surface of the high melting point metal layer is covered by the embedded conductive pattern.