# US 10,455,689 B2 · Mating backplane for high speed, high density electrical connector

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,455,689 B2
- Document ID: US10455689B2
- Status: Granted
- Kind: B2
- Application number: 16/032,284
- Filed: 2018-07-11
- Published: 2018-11-08
- Granted: 2019-10-22
- Earliest claimed: 2014-11-21
- Assignees: Amphenol Corporation
- Applicants: Amphenol Corporation
- Inventors: Mark W. Gailus; Marc B. Cartier, Jr.; Vysakh Sivarajan; David Levine
- Web page: https://patentgrep.com/patent/US10455689B2

## CPC

- H05K 1/0222: {for shielding around a single via or around a group of vias, e.g. coaxial vias or vias surrounded by a grounded via fence}
- H01R 43/205: {with a panel or printed circuit board}
- H05K 1/0216: {Reduction of cross-talk, noise or electromagnetic interference (grounding H05K1/0215)}
- H05K 1/0219: {Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors}
- H05K 1/025: {Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance (H05K1/024 and H05K1/0243 take precedence; for semiconductor devices H10W44/20)}
- H05K 1/0251: {related to vias or transitions between vias and transmission lines}
- H05K 1/0253: {Impedance adaptations of transmission lines by special lay-out of power planes, e.g. providing openings (H05K1/0251 takes precedence)}
- H05K 1/0298: {Multilayer circuits}
- H05K 1/115: {Via connections; Lands around holes or via connections (H05K1/112 takes precedence)}
- H05K 3/0047: {Drilling of holes}
- H05K 3/4038: {Through-connections; Vertical interconnect access [VIA] connections (H05K3/403, H05K3/42 take precedence)}
- H05K 3/429: {Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers}
- H05K 2201/07: Electric details
- H05K 2201/09063: Holes or slots in insulating substrate not used for electrical connections
- H05K 2201/09318: Core having one signal plane and one power plane
- H05K 2201/09545: Plated through-holes or blind vias without lands
- H05K 2201/096: Vertically aligned vias, holes or stacked vias
- H05K 2201/097: Alternating conductors, e.g. alternating different shaped pads, twisted pairs; Alternating components
- H05K 2201/09718: Clearance holes
- H05K 2201/09845: Stepped hole, via, edge, bump or conductor
- H05K 2201/09854: Hole or via having special cross-section, e.g. elliptical
- H05K 2201/10189: Non-printed connector
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H01R: ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS

## Abstract

A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns including first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; ground vias extending through at least the attachment layers, the ground vias including ground conductors; and shadow vias located adjacent to each of the first and second signal vias, wherein the shadow vias are free of conductive material in the attachment layers. The printed circuit board may further include slot vias extending through the attachment layers and located between via patterns.

## Claims

### Claim 1

A printed circuit board comprising:
a plurality of layers including conductive layers separated by dielectric layers;
first and second signal vias forming a differential signal pair, the first and second signal vias extending through one or more of the plurality of layers; and
shadow vias associated with each of the signal vias, the shadow vias extending through one or more of the plurality of layers, wherein the shadow vias have a first diameter above a predetermined depth in the plurality of layers and a second diameter, different from the first diameter, below the predetermined depth in the plurality of layers.

### Claim 2 (depends on 1)

The printed circuit board as defined in claim 1, wherein the shadow vias include shadow vias located on opposite sides of each of the first and second signal vias.

### Claim 3 (depends on 1)

The printed circuit board as defined in claim 1, wherein the shadow vias include shadow vias located on a line through the first and second signal vias.

### Claim 4 (depends on 1)

The printed circuit board as defined in claim 1, further comprising ground vias extending through one or more of the plurality of layers.

### Claim 5 (depends on 1)

The printed circuit board as defined in claim 1, wherein the shadow vias are free of conductive material in one or more of the plurality of layers.

### Claim 6 (depends on 1)

The printed circuit board as defined in claim 1, wherein the shadow vias are plated or filled with a conductive material.

### Claim 7 (depends on 1)

The printed circuit board as defined in claim 1, wherein the shadow vias include conductive material that interconnects ground planes of two or more of the plurality of layers.

### Claim 8 (depends on 1)

The printed circuit board as defined in claim 1, wherein the shadow vias are free of conductive material to a predetermined depth in the plurality of layers.

### Claim 9 (depends on 1)

The printed circuit board as defined in claim 1, wherein the shadow vias include shadow vias located on opposite sides of the first and second signal vias and additional shadow vias located on a line through the first and second signal vias.

### Claim 10 (depends on 1)

The printed circuit board as defined in claim 1, wherein the shadow vias have smaller diameters than the first and second signal vias in one or more layers of the plurality of layers.

### Claim 11

A method for making a printed circuit board, comprising:
forming a plurality of layers including conductive layers separated by dielectric layers;
forming first and second signal vias extending through one or more of the plurality of layers; and
forming shadow vias associated with each of the first and second signal vias, the shadow vias extending through one or more of the plurality of layers, wherein forming shadow vias includes forming the shadow vias with a first diameter above a predetermined depth in the plurality of layers and forming the shadow vias with a second diameter, different from the first diameter, below the predetermined depth in the plurality of layers.

### Claim 12 (depends on 11)

The method as defined in claim 11, wherein forming shadow vias includes forming shadow vias located on opposite sides of each of the first and second signal vias.

### Claim 13 (depends on 11)

The method as defined in claim 11, wherein forming shadow vias includes forming shadow vias located on a line through the first and second signal vias.

### Claim 14 (depends on 11)

The method as defined in claim 11, wherein forming shadow vias includes forming shadow vias that are free of conductive material.

### Claim 15 (depends on 11)

The method as defined in claim 11, wherein forming shadow vias includes forming shadow vias that are plated or filled with a conductive material.

### Claim 16 (depends on 11)

The method as defined in claim 11, wherein forming shadow vias includes forming shadow vias with conductive material that interconnects two or more of the plurality of layers.

### Claim 17 (depends on 11)

The method as defined in claim 11, wherein forming shadow vias includes forming shadow vias free of conductive material to a predetermined depth in the plurality of layers.

### Claim 18 (depends on 11)

The method as defined in claim 11, wherein forming shadow vias includes forming shadow vias located on opposite sides of the first and second signal vias and forming additional shadow vias located on a line through the first and second signal vias.

### Claim 19 (depends on 11)

The method as defined in claim 11, further comprising forming ground vias extending through one or more of the plurality of layers.

### Claim 20 (depends on 11)

The method as defined in claim 11, wherein the shadow vias are formed with smaller diameters than the first and second signal vias in one or more layers of the plurality of layers.