# US 10,455,535 B2 · Method and system for link synchronization in an LTE-TDD architecture > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,455,535 B2 - Document ID: US10455535B2 - Status: Granted - Kind: B2 - Application number: 15/820,299 - Filed: 2017-11-21 - Published: 2018-08-09 - Granted: 2019-10-22 - Earliest claimed: 2015-04-03 - Assignees: Dali Systems Co. Ltd. - Applicants: Dali Systems Co. Ltd. - Inventors: Wan-Jong Kim; Shawn Patrick Stapleton - Web page: https://patentgrep.com/patent/US10455535B2 ## CPC - H04W 56/0095: {estimated based on signal strength} - H04L 25/03: Shaping networks in transmitter or receiver, e.g. adaptive shaping networks - H04L 27/2656: {Frame synchronisation, e.g. packet synchronisation, time division duplex [TDD] switching point detection or subframe synchronisation} - H04L 27/2675: {Pilot or known symbols} - H04W 56/00: Synchronisation arrangements - H04W 56/001: {Synchronization between nodes} - H04W 88/085: {Access point devices with remote components} - H04L 5/0048: {Allocation of pilot signals, i.e. of signals known to the receiver (allocation of control signalling H04L5/0053; use of control signalling H04L5/0091)} - H04L 5/0053: {Allocation of signalling, i.e. of overhead other than pilot signals} - H04L 5/14: Two-way operation using the same type of signal, i.e. duplex - H04L 5/1469: {using time-sharing} - H04W: WIRELESS COMMUNICATION NETWORKS (broadcast communication H04H; communication systems using wireless links for non-selective communication, e.g. wireless extensions H04M1/72) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract A method of detecting a synchronization switching pulse using a power detector in a time division duplexing (TDD) system includes receiving an input signal, detecting a power level associated with the input signal using a digital power meter, and determining a configuration associated with the input signal. The method also includes determining that a pulse width associated with the input signal is greater than a threshold, determining an offset associated with a special subframe configuration, and generating an estimated sync pulse. The method further includes forming a regenerated sync pulse, determining an error between the estimated sync pulse and the regenerated sync pulse, determining that the error is less than a threshold, and providing a lock detect. ## Claims ### Claim 1 A method of generating a sync switching pulse in a time division duplexing (TDD) system, the method comprising: receiving an input signal at an input port of a digital power meter; receiving, at the digital power meter, a power threshold level; determining, by the digital power meter, that a power level associated with the input signal exceeds the power threshold level; generating the sync switching pulse in response to the power level associated with the input signal; determining an error based on the input signal and the sync switching pulse; generating a reset pulse based on the error; and shifting the sync switching pulse in response to the reset pulse. ### Claim 2 (depends on 1) The method of claim 1, further comprising: determining the sync switching pulse is associated with a logic high; and transmitting a signal associated with the input signal on a downlink path. ### Claim 3 (depends on 1) The method of claim 1, further comprising: determining the sync switching pulse is associated with a logic low; and transmitting a signal associated with the input signal on an uplink path. ### Claim 4 (depends on 1) The method of claim 1, wherein the input signal is from a base station. ### Claim 5 (depends on 1) The method of claim 1, wherein generating the sync switching pulse in response to the power level associated with the input signal further comprises determining, for the input signal, one or more pulse widths. ### Claim 6 (depends on 5) The method of claim 5, wherein at least one of the one or more pulse widths is greater than a pulse width threshold. ### Claim 7 (depends on 1) The method of claim 1, wherein generating the sync switching pulse in response to the power level associated with the input signal further comprises: determining a special subframe configuration associated with the input signal; and forming a regenerated sync pulse based on the special subframe configuration associated with the input signal; and providing the regenerated sync pulse as the sync switching pulse. ### Claim 8 (depends on 1) The method of claim 1, further comprising: determining the error is less than a predefined threshold; and provide a lock detect signal. ### Claim 9 A system for generating synchronized signals, the system comprising: an input port configured to receive an input signal, a digital power meter configured to determine that a power level associated with the input signal exceeds a power threshold level and output an estimated sync pulse; an edge detector configured to detect a number of rising edges and a number of falling edges associated with the estimated sync pulse; a counter configured to determine location data associated with the number of rising edges and the number of falling edges; a memory configured to store the number of rising edges, the number of falling edges, and the location data; a processor coupled to the memory, wherein the number of rising edges, the number of falling edges, and the location data are processed using a sync detection algorithm; and a sync pulse regenerator coupled to the processor and configured to generate a sync pulse in response to the number of rising edges, the number of falling edges, and the location data. ### Claim 10 (depends on 9) The system of claim 9 further comprising: a second sync pulse regenerator coupled to the processor and configured to generate a remote sync pulse in response to the number of rising edges, the number of falling edges, and the location data. ### Claim 11 (depends on 9) The system of claim 9 further comprising an error detector coupled to the sync pulse regenerator and the digital power meter, wherein the error detector is configured to determine an error based on the estimated sync pulse and the sync pulse. ### Claim 12 (depends on 11) The system of claim 11, wherein the error detector is coupled to the processor and configured to determine the error is below an error threshold and output a lock enable signal to the processor. ### Claim 13 (depends on 11) The system of claim 11, wherein the error detector is coupled to the processor and configured to determine the error exceeds an error threshold, and wherein the processor is configured to cause the sync pulse regenerator to shift the sync pulse in response to the error. ### Claim 14 (depends on 9) The system of claim 9 wherein the sync pulse regenerator is operable to generate a Time Division Duplexing-Long Term Evolution (TDD-LTE) frame structure defined sync pulse with predefined time durations and a predetermined offset time. ### Claim 15 (depends on 9) The system of claim 9 wherein the input signal is received at a base station input port.