# US 10,455,529 B2 · Multi-standard transmitter architecture with digital upconvert stage and gallium nitride (GAN) amplifier circuit

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- Number: US 10,455,529 B2
- Document ID: US10455529B2
- Status: Granted
- Kind: B2
- Application number: 15/974,809
- Filed: 2018-05-09
- Published: 2018-11-15
- Granted: 2019-10-22
- Earliest claimed: 2017-05-09
- Assignees: Khalifa University of Science and Technology
- Applicants: Khalifa University of Science and Technology
- Inventors: Mihai Sanduleanu; Shoeb Shaikh
- Web page: https://patentgrep.com/patent/US10455529B2

## CPC

- H04W 52/52: using AGC [Automatic Gain Control] circuits or amplifiers
- H03F 1/0227: {using supply converters}
- H03F 1/0288: {using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers}
- H03F 1/0294: {using vector summing of two or more constant amplitude phase-modulated signals}
- H03F 3/195: in integrated circuits
- H03F 3/2178: {using more than one switch or switching amplifier in parallel or in series (H03F3/2173, H03F3/2175 take precedence)}
- H03F 3/265: {with field-effect transistors only}
- H03F 3/45183: {Long tailed pairs (H03F3/4521, H03F3/45237 take precedence)}
- H03F 3/68: Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics {(power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602)}
- H04B 1/04: Circuits
- H04B 1/0475: {with means for limiting noise, interference or distortion (H04B1/0483 takes precedence)}
- H04W 52/42: in systems with time, space, frequency or polarisation diversity
- H03F 2200/102: A non-specified detector of a signal envelope being used in an amplifying circuit
- H03F 2200/111: the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not
- H04B 2001/045: {with means for improving efficiency}
- H04W: WIRELESS COMMUNICATION NETWORKS (broadcast communication H04H; communication systems using wireless links for non-selective communication, e.g. wireless extensions H04M1/72)
- H03F: AMPLIFIERS
- H04B: TRANSMISSION

## Abstract

A multi-standard transmitter architecture with digitally upconverted intermediate frequency (IF) outphased signals is disclosed. The transmitter architecture includes a Gallium Nitride (GaN) power amplifier (PA) circuit having a Current Mode Class-D (CMCD) configuration. The GaN PA circuit includes a lower switching device electrically coupled to an input to receive an input RF signal and an upper switching device to switchably electrically couple the first switching device to a power supply to drive an antenna circuit based on the input RF signal. Thus, a reconfigurable transmitter architecture is disclosed that utilizes a high-speed Gallium Nitride (GaN) driver to achieve a peak drain efficiency of at least 85% while delivering output power of 10 W at 1 GHz frequency, for example.

## Claims

### Claim 1

A transmitter system comprising:
an output stage comprising:
a Gallium Nitride (GaN) power amplifier (PA) circuit having a Modified Current Mode Class-D (CMCD) configuration, the GaN PA circuit including:
a lower switching device electrically coupled to an input to receive an input RF signal;
an upper switching device to switchably couple the first switching device to a power supply to drive an antenna circuit based on the input RF signal; and
wherein the lower and upper switching devices form a first transistor cascode arrangement;
wherein the GaN PA circuit operates at a peak drain efficiency between 80% to 85% when operating at a frequency of substantially 1 Gigahertz (GHz) and has an output power substantially equal to 10 Watts (W).

### Claim 2 (depends on 1)

The transmitter system of claim 1, wherein the GaN PA circuit includes a second cascode transistor arrangement, the first and second cascode switching arrangements forming an inverse CMCD configuration.

### Claim 3 (depends on 1)

The transmitter system of claim 1, wherein the upper switching device of the first cascode transistor arrangement is 1.22±0.2 millimeters wide.

### Claim 4 (depends on 1)

The transmitter system of claim 1, wherein the upper switching device and the lower switching device of the first cascode transistor arrangement comprise GaN field-effect transistor devices (FETs).

### Claim 5 (depends on 1)

The transmitter system of claim 1, wherein the upper switching device and/or the lower switching device comprise high-voltage GaN high electron mobility transistor (HEMT) devices.

### Claim 6 (depends on 1)

The transmitter system of claim 1, further comprising the antenna driving circuit, and wherein the antenna driving circuit is implemented on a different chip than the GaN PA circuit.

### Claim 7 (depends on 1)

The transmitter system of claim 1, further comprising a digital upconvert stage, the digital upconvert stage comprising:
an intermediate frequency (IF) processor for receiving a first signal (I(t)) representing an in-phase component of an output waveform and a second signal (Q(t)) representing the quadrature component of the output waveform, and outputting a first and second set of outphased IF signals; and
digital upconvert circuitry to receive the first and second set of outphased IF signals and digitally upconvert the first and second set of outphased IF signals to provide the RF signal for driving the GaN PA circuit.

### Claim 8 (depends on 7)

The transmitter system of claim 7, wherein the digital upconvert stage is implemented as a complementary metal-oxide semiconductor (CMOS) application-specific integrated circuit (ASIC).

### Claim 9 (depends on 7)

The transmitter system of claim 7, wherein the digital upconvert stage and the output stage are electrically coupled via a 50 ohm terminated transmission line.

### Claim 10

A method for digitally upconverting an intermediate frequency (IF) signal, the method comprising:
receiving a first outphased signal (VI) and a second outphased signal (VQ),
multiplying the first outphased signal (VI) with a first multi-level digital clock signal (LOI(t)) to provide a first digitally upconverted signal at a first carrier frequency; and
multiplying the second outphased signal (VQ) with a second multi-level digital clock signal (LOI(q)) to provide a second digitally upconverted signal at the first carrier frequency;
wherein the first and second multi-level digital clock signals each comprise signal levels of −1V, 0V, and +1V.

### Claim 11 (depends on 10)

The method of claim 10, further comprising summing the first and second outphased signals to derive an RF signal to provide to a PA stage based on the following equation:
Y1(t)=VI×LOI(t)+VQ×LOQ(t).

### Claim 12

A transmitter system comprising:
an output stage comprising:
a Gallium Nitride (GaN) power amplifier (PA) circuit having a Modified Current Mode Class-D (CMCD) configuration, the GaN PA circuit including:
a lower switching device electrically coupled to an input to receive an input RF signal;
an upper switching device to switchably couple the first switching device to a power supply to drive an antenna circuit based on the input RF signal; and
wherein the lower and upper switching devices form a first transistor cascode arrangement; and
wherein the upper switching device of the first cascode transistor arrangement is 1.22±0.2 millimeters wide.

### Claim 13 (depends on 12)

The transmitter system of claim 12, wherein the GaN PA circuit operates at a peak drain efficiency between 80% to 85% when operating at a frequency of substantially 1 Gigahertz (GHz) and an output power substantially equal to 10 Watts (W).

### Claim 14 (depends on 12)

The transmitter system of claim 12, wherein the upper switching device and the lower switching device of the first cascode transistor arrangement comprise GaN field-effect transistor devices (FETs).

### Claim 15 (depends on 12)

The transmitter system of claim 12, wherein the upconvert circuit is implemented as a complementary metal-oxide semiconductor (CMOS) application-specific integrated circuit (ASIC) and is electrically coupled to the output stage via a 50 ohm terminated transmission line.

### Claim 16 (depends on 12)

The transmitter system of claim 12, further comprising an upconvert circuit having a plurality of stages to digitally upconvert outphased IF signals and provide an upconverted outphased digital RF signal; and
wherein the output stage further comprises:
an amplification circuit to receive the outphased digital RF signal and generate a driving signal based on outphased digital RF signal; and
a driving circuit comprising an inverter circuit to drive said GaN PA circuit based on the driving signal.

### Claim 17

A transmitter system comprising:
an output stage comprising:
a Gallium Nitride (GaN) power amplifier (PA) circuit having a Modified Current Mode Class-D (CMCD) configuration, the GaN PA circuit including:
a lower switching device electrically coupled to an input to receive an input RF signal;
an upper switching device to switchably couple the first switching device to a power supply to drive an antenna circuit based on the input RF signal; and
wherein the lower and upper switching devices form a first transistor cascode arrangement; and
wherein the GaN PA circuit includes a second cascode transistor arrangement, the first and second cascode switching arrangements forming an inverse CMCD configuration.

### Claim 18 (depends on 17)

The transmitter system of claim 17, wherein the upper switching device of the first cascode transistor arrangement is 1.22±0.2 millimeters wide.

### Claim 19 (depends on 17)

The transmitter system of claim 17, wherein the GaN PA circuit operates at a peak drain efficiency between 80% to 85% when operating at a frequency of substantially 1 Gigahertz (GHz) and has an output power substantially equal to 10 Watts (W).

### Claim 20

A transmitter system comprising:
an output stage comprising:
a Gallium Nitride (GaN) power amplifier (PA) circuit having a Modified Current Mode Class-D (CMCD) configuration, the GaN PA circuit including:
a lower switching device electrically coupled to an input to receive an input RF signal;
an upper switching device to switchably couple the first switching device to a power supply to drive an antenna circuit based on the input RF signal; and
wherein the lower and upper switching devices form a first transistor cascode arrangement;
wherein the output stage further comprises a two-stage driver circuit, the two-stage driver circuit comprising:
a first stage to receive a digital outphased intermediate frequency (IF) signal and generate a driving signal based on the digital outphased IF signal;
a second stage comprising an inverter circuit to couple to the input of the GaN PA circuit and drive the GaN PA circuit based on the driving signal; and
wherein the driving signal provides a 0 to VDD swing sufficient to switch on the lower switching device of the first cascode transistor arrangement.

### Claim 21 (depends on 20)

The transmitter system of claim 20, wherein the two-stage driver circuit and the GaN PA driving circuit are implemented on the same chip.