# US 10,455,331 B2 · MEMS transducer amplifiers

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- Number: US 10,455,331 B2
- Document ID: US10455331B2
- Status: Granted
- Kind: B2
- Application number: 15/916,597
- Filed: 2018-03-09
- Published: 2018-09-20
- Granted: 2019-10-22
- Earliest claimed: 2017-03-16
- Assignees: Cirrus Logic, Inc.
- Applicants: Cirrus Logic International Semiconductor Ltd.
- Inventors: Hynek Saman; James Thomas Deas
- Web page: https://patentgrep.com/patent/US10455331B2

## CPC

- H04R 19/04: Microphones (H04R19/01 takes precedence)
- H03F 1/26: Modifications of amplifiers to reduce influence of noise generated by amplifying elements
- H03F 3/187: in integrated circuits
- H03F 3/45475: {using IC blocks as the active amplifying circuit}
- H03F 3/45636: {by using feedback means (H03F3/45744 takes precedence)}
- H03F 3/505: {with field-effect devices}
- H04R 19/005: {using semiconductor materials}
- H03F 2200/03: the amplifier being designed for audio applications
- H03F 2200/213: A variable capacitor being added in the input circuit, e.g. base, gate, of an amplifier stage
- H04R 2201/003: Mems transducers or their use
- H04R: LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; ELECTRIC HEARING AIDS; PUBLIC ADDRESS SYSTEMS (producing sounds with frequency not determined by supply frequency G10K)
- H03F: AMPLIFIERS

## Abstract

An amplifier circuit has a transducer biasing node for outputting a transducer bias voltage for biasing the capacitive transducer and a signal node for receiving the input signal. An amplifier arrangement comprising a feedback resistor network provides an amplified output signal. A voltage buffer provides a buffered bias voltage at a buffer node which is connected to a terminal of the feedback resistor network, to at least partly define the quiescent level of the output signal. The buffer node is electrically coupled to the transducer biasing node via a capacitance which may form part of a bias filter.

## Claims

### Claim 1

An amplifier circuit for amplifying an input signal from a capacitive transducer comprising:
a transducer biasing node for outputting a transducer bias voltage for biasing the capacitive transducer;
a signal node for receiving the input signal from the capacitive transducer;
an amplifier arrangement coupled to the signal node to amplify the input signal and generate an output signal at an output node, the amplifier arrangement comprising a feedback resistor network;
a voltage buffer configured to generate a buffered bias voltage at a buffer node;
wherein a terminal of the feedback resistor network is electrically coupled to the buffer node to receive said buffered bias voltage; and
a first capacitance is electrically coupled between the transducer biasing node and the buffer node.

### Claim 2 (depends on 1)

An amplifier circuit as claimed in claim 1 wherein the amplifier arrangement comprises an input transistor coupled so as to be driven by the input signal at the signal node.

### Claim 3 (depends on 2)

An amplifier circuit as claimed in claim 2 wherein the amplifier arrangement further comprises a first amplifier and the feedback resistor network comprises first and second resistors, wherein:
the input transistor comprises:
a gate terminal coupled to the signal node;
a drain terminal coupled to a first input of the first amplifier; and
a source terminal connected to an output of the first amplifier via the first resistor;
a second input of the first amplifier is connected to receive a defined reference voltage;
the output of the first amplifier is coupled to the output node;
the first resistor is coupled between the output of the first amplifier and the source terminal of the input transistor; and
the second resistor is coupled between the buffer node and the source terminal of the input transistor.

### Claim 4 (depends on 3)

An amplifier circuit as claimed in claim 3 further comprising a first current source coupled to the source terminal of the input transistor for sourcing a defined current.

### Claim 5 (depends on 4)

An amplifier circuit as claimed in claim 4 comprising an additional resistor connected between the drain terminal of the input transistor and a defined voltage.

### Claim 6 (depends on 3)

An amplifier circuit as claimed in claim 3 further comprising a first current sink coupled to the drain terminal of the input transistor for sinking a defined current.

### Claim 7 (depends on 3)

An amplifier circuit as claimed in claim 3 wherein the voltage buffer comprises a buffer transistor coupled to be driven by an input quiescent bias voltage.

### Claim 8 (depends on 7)

An amplifier circuit as claimed in claim 7 wherein the voltage buffer further comprises a second amplifier, wherein:
a gate terminal of the buffer transistor is coupled to receive the input quiescent bias voltage,
a drain terminal of the buffer transistor is coupled to an input of the second amplifier;
a source terminal of the buffer transistor is coupled to the output of the second amplifier and to the buffer node; and
a second input of the second amplifier is connected to receive the defined reference voltage.

### Claim 9 (depends on 8)

An amplifier circuit as claimed in claim 8 wherein the output of the second amplifier is connected to the buffer node and the source terminal of the buffer transistor via a third resistor.

### Claim 10 (depends on 9)

An amplifier circuit as claimed in claim 9 wherein the output of the second amplifier is output at a complementary output node as a complementary output signal.

### Claim 11 (depends on 1)

An amplifier circuit as claimed in claim 1 wherein the signal node is connected, in use, to a signal node bias voltage via a signal node impedance.

### Claim 12 (depends on 1)

An amplifier circuit as claimed in claim 1 further comprising:
a potential divider having first and second ends, the first end coupled to the signal node and configured to generate an attenuated version of the signal at the signal node;
a second amplifier arrangement coupled to the potential divider to amplify the attenuated input signal and generate a second output signal at a second output node, the second amplifier arrangement comprising a second feedback resistor network; and
wherein a terminal of the second feedback resistor network is electrically coupled to the buffer node to receive said buffered bias voltage; and
wherein the second end of the potential divider is electrically coupled to buffer node.

### Claim 13 (depends on 12)

An amplifier circuit as claimed in claim 12 wherein the potential divider is a capacitive potential divider.

### Claim 14 (depends on 1)

An amplifier circuit as claimed in claim 1 wherein the first capacitor forms part of a filter for filtering the transducer bias voltage.

### Claim 15 (depends on 1)

An amplifier circuit as claimed in claim 1 comprising a capacitive transducer connected between the transducer biasing node and the signal node.

### Claim 16 (depends on 15)

An amplifier circuit as claimed in claim 15 where the capacitive transducer is a MEMS capacitive transducer.

### Claim 17 (depends on 15)

An amplifier circuit as claimed in claim 15 wherein the capacitive transducer is integrated with the amplifier circuit in an integrated circuit.

### Claim 18 (depends on 1)

An electronic device comprising an amplifier circuit as claimed in claim 1 wherein the electronic device is at least one of: a communications device; a mobile or cellular telephone; a smartphone device; a computing device; a laptop, notebook or tablet computer; a portable device; a battery powered device; a wearable device; a voice-operated device; a gaming device.

### Claim 19

An amplifier apparatus comprising:
a MEMS capacitive transducer connected between a transducer biasing node and a signal node;
an amplifier arrangement coupled to the signal node to amplify the input signal, the amplifier arrangement comprising a feedback resistor network; and
a voltage buffer configured to generate a buffered bias voltage at a buffer node;
wherein a terminal of the feedback resistor network is electrically coupled to the buffer node to receive said buffered bias voltage;
a signal path between the buffer node and the transducer biasing node comprising a first capacitor.

### Claim 20

An amplifier circuit for amplifying an input signal from a capacitive transducer comprising:
a signal node for receiving the input signal;
a transducer biasing node for outputting a transducer bias voltage for biasing the capacitive transducer;
an input transistor having a gate terminal coupled to the signal node;
an amplifier having an input connected to a drain terminal of the input transistor and an output connected to a source terminal of the input transistor via a first feedback resistor;
a defined current element for defining a gate-to-drain current through the input transistor;
a voltage buffer configured to generate a buffered bias voltage at a buffer node;
a second feedback resistor connected between the buffer node and the source terminal of the input transistor; and
a first capacitance electrically coupled between the transducer biasing node and the buffer node.