# US 10,454,847 B2 · Radio frequency signal router

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- Number: US 10,454,847 B2
- Document ID: US10454847B2
- Status: Granted
- Kind: B2
- Application number: 15/791,496
- Filed: 2017-10-24
- Published: 2018-03-29
- Granted: 2019-10-22
- Earliest claimed: 2012-04-16
- Assignees: Evertz Microsystems Ltd.
- Applicants: Evertz Microsystems Ltd.
- Inventors: Daniel Baldor
- Web page: https://patentgrep.com/patent/US10454847B2

## CPC

- H04L 49/15: Interconnection of switching modules
- H04L 45/60: Router architectures
- H04L 49/1515: Non-blocking multistage, e.g. Clos
- H04L 49/1523: {Parallel switch fabric planes}
- H04L 49/552: by ensuring the integrity of packets received through redundant connections
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A RF router for routing n input signals to m destinations, where the router comprises a backplane coupled to a plurality of RF input terminals, a plurality of RF output terminals, a plurality of splitters and a plurality of connectors. The backplane is also coupled to a controller and a plurality of connectors for receiving a plurality of switching matrices. The RF router comprises a plurality of u×v input switch matrices, a plurality of p×q intermediate switch matrices and a plurality of r×s output switch matrices, where at least one of the plurality of u×v input switch matrices, the plurality of p×q intermediate switch matrices and the plurality of r×s output switch matrices are redundant.

## Claims

### Claim 1

A radio frequency (RF) router comprising:
a plurality of RF input terminals, wherein each RF input terminal is configured to receive an input RF signal;
a plurality of u×v input switch matrices coupled to the plurality of RF input terminals, each of the plurality of u×v input switch matrices having u inputs and v outputs;
a plurality of p×q intermediate switch matrices, each of the plurality of p×q intermediate switch matrices having p inputs and q outputs, wherein inputs of each p×q intermediate switch matrices are coupled to outputs of the u×v input switch matrices such that each input of each p×q intermediate switch matrix is coupled to exactly one output of the plurality of u×v input switch matrices; and
a plurality of r×s output switch matrices, each of the plurality of r×s output switch matrices having r inputs and s outputs, wherein inputs of each r×s output switch matrix are coupled to outputs of the p×q intermediate switch matrices such that each input of each r×s output switch matrix is coupled to exactly one output of the plurality of p×q intermediate switch matrices,
wherein at least one of the plurality of u×v input switch matrices, at least one of the plurality of p×q intermediate switch matrices and at least one of the plurality of output switch matrices are redundant.

### Claim 2 (depends on 1)

The RF router of claim 1, wherein the inputs of each p×q intermediate switch matrix are coupled to different u×v input switch matrices.

### Claim 3 (depends on 1)

The RF router of claim 1, wherein the inputs of each r×s output switch matrix are coupled to different p×q intermediate switch matrices.

### Claim 4 (depends on 1)

The RF router of claim 1, wherein the RF router has at least 64 RF input terminals.

### Claim 5 (depends on 4)

The RF router of claim 4, wherein the RF router has at least 64 RF output terminals.

### Claim 6 (depends on 5)

The RF router of claim 5, wherein when the RF router has 64 RF input terminals and 64 RF output terminals, the RF router comprises 16 u×v input switch matrices, 16 p×q intermediate switch matrices and 16 r×s output switch matrices, wherein the plurality of u×v input switch matrices, the plurality of p×q intermediate switch matrices and the plurality of r×s output switch matrices are 8×8 switch matrices.

### Claim 7 (depends on 5)

The RF router of claim 5, wherein when the RF router has 64 RF input terminal and 128 RF output terminals, the RF router comprises 16 u×v input switch matrices, 16 p×q intermediate switch matrices and 32 r×s output switch matrices, wherein the plurality of u×v input switch matrices and the plurality of r×s output switch matrices are 8×8 switch matrices, and the plurality of p×q intermediate switch matrices are 8×16 switch matrices.

### Claim 8 (depends on 4)

The RF router of claim 4, wherein when the RF router has 128 RF input terminals and 128 RF output terminals, the RF router comprises 32 u×v input switch matrices, 16 p×q intermediate switch matrices and 32 r×s output switch matrices, wherein the plurality of u×v input switch matrices and the plurality of r×s output switch matrices are 8×8 switch matrices, and the plurality of p×q intermediate switch matrices are 16×16 switch matrices.

### Claim 9 (depends on 1)

The RF router of claim 1, wherein each RF input terminal has an external signal impedance and wherein the RF router has an internal signal impedance, and wherein the RF router further comprises an impedance matching stage coupled between each RF input terminal and a corresponding splitter, wherein the impedance matching stage matches the external signal impedance to the corresponding RF input terminal and the internal signal impedance to the corresponding splitter.

### Claim 10 (depends on 1)

The RF router of claim 1, wherein at least some r×s output switch matrices comprise an automatic gain control stage, wherein each automatic gain control stage operates to adjust the gain of an incoming signal.

### Claim 11 (depends on 10)

The RF router of claim 10, wherein at least some r×s output switch matrices comprise an equalization stage coupled to the automatic gain control stage, wherein each of the equalization stage is configurable to equalize the incoming RF signal.

### Claim 12 (depends on 1)

The RF router of claim 1, wherein at least some of the u×v input switch matrix comprise an equalization stage to equalize the input RF signal.

### Claim 13 (depends on 1)

The RF router of claim 1, wherein at least some p×q intermediate switch matrices comprise an equalization stage for equalizing an incoming RF signal.

### Claim 14 (depends on 1)

The RF router of claim 1, further comprising a plurality of connectors for receiving the plurality of u×v input switch matrices, the plurality of p×q intermediate switch matrices and the plurality of r×s output switch matrices, wherein each connector is a self-terminating connector configured to close opposing pins of the connector to provide an impedance in an unconnected mode.

### Claim 15 (depends on 1)

The RF router of claim 1, wherein at least one input switch matrix, at least one p×q intermediate switch matrix and at least one r×s output switch matrix comprise a sensor configured to detect removal of the u×v input switch matrices, p×q intermediate switch matrices and r×s output switch matrices from the plurality of connectors.

### Claim 16 (depends on 15)

The RF router of claim 15, wherein at least one input switch matrix, at least one p×q intermediate switch matrix and at least one r×s output switch matrix comprise a module ejector and wherein the sensor is configured to detect whether the module ejector is in an open or close state to detect removal of the u×v input switch matrices, p×q intermediate switch matrices and r×s output switch matrices to the plurality of connectors.

### Claim 17 (depends on 16)

The RF router of claim 16, wherein the sensor is a capacitive sensor.

### Claim 18 (depends on 1)

The RF router of claim 1, wherein at least one input switch matrix, at least one p×q intermediate switch matrix and at least one r×s output switch matrix comprise a sensor configured to detect insertion of the u×v input switch matrices, p×q intermediate switch matrices and r×s output switch matrices to the plurality of connectors.

### Claim 19 (depends on 1)

The RF router of claim 1, wherein the input RF terminals and the output RF terminals comprise a BNC connector.