US 10,453,894 B2Granted

Systems and methods for fabrication of superconducting integrated circuits

AssigneeD-Wave Systems Inc.

InventorsEric Ladizinsky, Geordie Rose, Jeremy P. Hilton, Eugene Dantsker, Byong Hyop Oh

Life of this patent

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Abstract

Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap connector.

Claims18

Dependent claims

A method of fabricating a superconducting integrated circuit, the method comprising:

depositing a dielectric layer to overlie a substrate, the dielectric layer including an exposed upper surface;
etching the exposed upper surface of the dielectric layer to form a trench in the dielectric layer, the etching including performing a photolithographic process;
depositing a metal layer to overlie the dielectric layer, the metal layer comprising a first and a second portion, the first portion of the metal layer deposited on an unetched portion of the exposed upper surface of the dielectric layer and the second portion of the metal layer deposited in the trench;
and
planarizing the metal layer to remove at least some of the first portion of the metal layer, wherein depositing a metal layer to overlie the dielectric layer includes depositing a material that superconducts at or below a critical temperature.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/956,404Filed 18 Apr 2018 · continuation
Priority: 27 Feb 2009
Published: US 2018/0308896 A125 Oct 2018
Granted: 22 Oct 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10N 69/00
Integrated devices, or assemblies of multiple devices, comprising at least one superconducting
B82Y 10/00
Nanotechnology for information processing, storage or transmission
H10D 1/474
Resistors having no potential barriers: comprising refractory metals, transition metals, noble metals, metal compounds or metal alloys, e.g. silicides
H10N 60/0156
Manufacture or treatment: of devices comprising Nb or an alloy of Nb with one or more of the elements of group IVB, e.g. titanium, zirconium or…

Family

Application61/156,377Us provisional application · filed 27 Feb 2009
PCT/US2010/025403Parent of this division · filed 25 Feb 2010
Application14/589,574Parent of this continuation · filed 5 Jan 2015
US 8,951,808 B2Parent of this division · filed 10 Feb 2015
Application15/289,782Parent of this continuation · filed 10 Oct 2016
US 9,490,296 B2Parent of this continuation · filed 8 Nov 2016
US 2018/0308896 A1Pre-grant publication · published 25 Oct 2018
US 9,978,809 B2Parent of this continuation
Application12/992,049Parent of this division
Application14/589,574Parent of this division
US 2011/0089405 A1Published application
US 2015/0187840 A1Published application
US 2017/0098682 A1Published application
US 10,453,894 B2This patent

From the US filing history. Foreign family members aren’t listed.