Shift register, gate driving circuit containing the same, and method for driving the same

A shift register, comprising:

• an input circuit, electrically connected to a triggering signal line that provides a triggering signal, a first clock signal line that provides a first clock signal, and a first node, configured for controlling whether the triggering signal is outputted to the first node based on the first clock signal;
• a control circuit comprising a first control unit and a second control unit, wherein:
• the first control unit including a third transistor, a fourth transistor, a fifth transistor, and a first capacitor, configured for controlling whether a turn-on signal is outputted to a second node,
• the third transistor has a gate electrode electrically connected to the first clock signal line, a source electrode electrically connected to a turn-on signal line that provides the turn-on signal, and a drain electrode electrically connected to a third node,
• the fourth transistor has a gate electrode electrically connected to a second clock signal line that provides a second clock signal, a source electrode electrically connected to the turn-on signal line, and a drain electrode electrically connected to a source electrode of the fifth transistor,
• the fifth transistor includes a gate electrode electrically connected to the third node, a drain electrode electrically connected to the second node, and the source electrode electrically connected to the drain electrode of the fourth transistor,
• the first capacitor includes a first terminal electrically connected to the turn-on signal line and a second terminal electrically connected to the third node, and
• the second control unit is electrically connected to a first signal line that provides a first signal, the first node and the second node, configured for controlling whether the first signal is outputted to the second node;
• and
• an output circuit, electrically connected to the first node, the second node, the first signal line, a second signal line that provides a second signal, and a driving signal output line that outputs a driving signal, configured for responding to signals at the first node and the second node, selecting one of the first signal and the second signal as the driving signal, and providing the driving signal to the driving signal output line.