Hybrid differential amplifier and method thereof

An apparatus comprising:

• a first hybrid differential amplifier configured to receive a first input signal and a second input signal and output a first output signal and a second output signal using a first cascode amplifier and a second cascode amplifier, respectively;
• and
• a second hybrid differential amplifier configured to receive a third input signal and a fourth input signal and output a third output signal and a fourth output signal using a third cascode amplifier and a fourth cascode amplifier, respectively;
• wherein:
• the first cascode amplifier and the third cascode amplifier are based on using PMOS (p-channel metal oxide semiconductor) transistors, the second cascode amplifier and the fourth cascode amplifier are based on using NMOS (n-channel metal oxide semiconductor) transistors, a DC (direct current) component of the first input signal is the same as a DC component of the third input signal, a DC component of the second input signal is the same as a DC component of the fourth input signal, an AC (alternating current) component of the first input signal is the same as an AC component of the fourth input signal, an AC component of the second input signal is the same as an AC component of the third input signal, and the AC component of the second input signal is an inversion of the AC component of the first input signal.

A method comprising:

• receiving a first voltage and a second voltage, wherein an AC (alternating current) component of the first voltage is an inversion of an AC component of the second voltage;
• converting the first voltage into a first current using a first common-source amplifier comprising a first PMOS (p-channel metal oxide semiconductor) transistor;
• converting the second voltage into a second current using a second common-source amplifier comprising a first NMOS (n-channel metal oxide semiconductor) transistor, wherein the first common-source amplifier and the second common-source amplifier share a common source node;
• relaying the first current into a third current using a first common-gate amplifier comprising a second PMOS transistor;
• relaying the second current into a fourth current using a second common-gate amplifier comprising a second NMOS transistor;
• and
• terminating the third current and the fourth current with a load,
• wherein the load comprises a first inductor inserted between the drain of the second PMOS transistor and a ground node and the first inductor is directly connected to the ground node, and a second inductor inserted between the drain of the second NMOS transistor and a power node and the second inductor is directly connected to the power node.