US 10,446,258 B2Granted

Methods and apparatus for providing redundancy in memory

AssigneeMicron Technology, Inc.

InventorsViolante Moschiano, Giovanni Santin, Maria-Luisa Gallese, Luigi Pilolli

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Abstract

Methods for providing redundancy in a memory include mapping a portion of first data associated with an address of the memory determined to indicate a defective memory cell to an address of a redundant area of the memory array, and writing second data to the memory array, wherein a portion of the second data is written to a column of the memory array associated with the address of the memory determined to indicate a defective memory cell for the first data. Apparatus include memory control circuitry configured to select a portion of data for mapping to a different address in response to an address indicating a defective memory cell, and further configured to select a different portion of data for a particular row than for a different row, wherein the particular row and the different row are associated with the same columns of the memory array.

Claims20

Dependent claims

A method for providing redundancy in a memory, wherein the memory has a memory array and one or more addresses of the memory array have been determined to indicate a defective memory cell, the method comprising:

loading first data for programming into a particular row of the memory array;
mapping a portion of the first data between an address of the memory array determined to indicate a defective memory cell of a particular column of the memory array and an address of a redundant area of the memory array;
loading second data for programming into a different row of the memory array, wherein the different row of the memory array includes a memory cell of the particular column of the memory array;
and
mapping a portion of the second data between an address of the memory array determined to indicate a defective memory cell of a different column of the memory array and an address of a redundant area of the memory array, and without mapping any portion of the second data between an address of the memory array of the particular column of the memory array and an address of a redundant area of the memory array.

2 more elements

An apparatus comprising:

a memory array having a redundant area, and having rows associated with access lines and columns associated with bit lines;
a page buffer for holding data prior to be programmed to the memory array or to be read from the memory array;
a memory block configured to store addresses of the memory array indicating a defective memory cell;
and
memory control circuitry configured to select a portion of data from the buffer for mapping to a different address of the buffer in response to an address indicating a defective memory cell;
wherein the memory control circuitry is further configured to select a different portion of data from the buffer for a particular row of the memory array than for a different row of the memory array;
wherein the memory control circuitry further comprises a logic function to select either a bit or a byte of data responsive to an address indicating a defective memory cell;
and
wherein the particular row of the memory array and the different row of the memory array are associated with the same columns of the memory array.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/721,994Filed 2 Oct 2017 · division
Priority: 12 Aug 2011
Published: US 2018/0047460 A115 Feb 2018
Granted: 15 Oct 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G11C 29/846
With improved access time or stability: by choosing redundant lines at an output stage
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
G11C 29/76
Masking faults in memories by using spares or by reconfiguring: using address translation or modifications
G11C 29/82
For an application-specific layout: for eeproms

Family

Application13/208,502Parent of this continuation · filed 12 Aug 2011
Application14/940,327Parent of this division · filed 13 Nov 2015
US 9,202,569 B2Parent of this continuation · filed 1 Dec 2015
US 2018/0047460 A1Pre-grant publication · published 15 Feb 2018
US 9,779,839 B2Parent of this division
Application14/940,327Parent of this continuation
US 2013/0039138 A1Published application
US 2016/0071619 A1Published application
US 10,446,258 B2This patent

From the US filing history. Foreign family members aren’t listed.