Controller to detect malfunctioning address of memory device
AssigneeRambus Inc.
InventorsAdrian E. Ong, Fan Ho
Life of this patent
Estimating the term…
Abstract
A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address.
Claims17
A packaged device comprising:
- a memory device implemented on a first chip;
- and
- a memory control unit implemented on a second chip and coupled to the memory device, the memory control unit comprising logic to:
- identify one or more primary memory cells of the memory device for repair;
- and
- initiate the repair of the identified one or more primary memory cells using secondary memory cells on the memory device after the memory device implemented on the first chip has been packaged with the memory control unit implemented on the second chip in the packaged device, wherein to initiate the repair, the logic to send a command comprising one or more memory addresses of the one or more primary memory cells to the memory device, the command to cause the memory device to store the one or more memory addresses in an address matching register on the memory device.
An apparatus comprising:
- a memory device implemented on a first chip;
- and
- an application specific integrated circuit (ASIC) implemented on a second chip and coupled to the memory device, the ASIC comprising logic to:
- identify one or more primary memory storage elements of the memory device for repair;
- and
- initiate the repair of the identified one or more primary memory storage elements using secondary storage elements on the memory device after the memory device implemented on the first chip has been packaged with the ASIC implemented on the second chip in a single package, wherein to initiate the repair, the logic to send a command comprising one or more memory addresses of the one or more primary memory cells to the memory device, the command to cause the memory device to store the one or more memory addresses in an address matching register on the memory device.
A memory controller comprising:
- an internal memory;
- a memory control unit coupled to the internal memory, the memory control unit comprising logic to:
- identify, for repair, one or more primary memory cells of a memory device implemented on a first chip and packaged with the memory control unit implemented on a second chip in a single package;
- and
- initiate the repair of the identified one or more primary memory cells using secondary memory cells of the memory device, wherein to initiate the repair, the logic to send a command comprising one or more memory addresses of the one or more primary memory cells to the memory device, the command to cause the memory device to store the one or more memory addresses in an address matching register on the memory device.
Dependencies are inferred from the claim text.