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US 10,443,046 B2Granted
Arrays of memory cells individually comprising a capacitor and an elevationally-extending transistor, methods of forming a tier of an array of memory cells, and methods of forming an array of memory cells individually comprising a capacitor and an elevationally-extending transistor
AssigneeMicron Technology, Inc.
InventorDurai Vishak Nirmal Ramaswamy
Life of this patent
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Abstract
A method of forming a tier of an array of memory cells within an array area, the memory cells individually comprising a capacitor and an elevationally-extending transistor, the method comprising using two, and only two, sacrificial masking steps within the array area of the tier in forming the memory cells. Other methods are disclosed, as are structures independent of method of fabrication.
Claims23
A tier of memory cells comprising:
- a first memory cell and a second memory cell laterally adjacent the first memory cell;
- the first memory cell comprising:
- a first capacitor and a first vertical transistor;
- the first vertical transistor comprising a first pillar comprising a channel and an upper source/drain region above the channel of the first vertical transistor, the channel of the first vertical transistor being above and electrically coupled to a digit line;
- and
- the first capacitor comprising a first bottom electrode directly against a lateral side of the upper source/drain region of the first vertical transistor;
- the second memory cell comprising:
- a second capacitor and a second vertical transistor;
- the second vertical transistor comprising a second pillar comprising a channel and an upper source/drain region above the channel of the second vertical transistor, the channel of the second vertical transistor being above and electrically coupled to the digit line;
- and
- the second capacitor comprising a second bottom electrode directly against a lateral side of the upper source drain region of the second vertical transistor;
- and
- the first capacitor and the second capacitor sharing a common top electrode.
10 more elements
Multiple stacked tiers of memory cells, individual of the tiers of memory cells comprising:
- a first memory cell and a second memory cell laterally adjacent the first memory cell;
- the first memory cell comprising:
- a first capacitor and a first vertical transistor;
- the first vertical transistor comprising a first pillar comprising a channel and an upper source/drain region above the channel of the first vertical transistor, the channel of the first vertical transistor being above and electrically coupled to a digit line;
- and
- the first capacitor comprising a first bottom electrode directly against a lateral side of the upper source/drain region of the first vertical transistor;
- the second memory cell comprising:
- a second capacitor and a second vertical transistor;
- the second vertical transistor comprising a second pillar comprising a channel and an upper source/drain region above the channel of the second vertical transistor, the channel of the second vertical transistor being above and electrically coupled to the digit line;
- and
- the second capacitor comprising a second bottom electrode directly against a lateral side of the upper source drain region of the second vertical transistor;
- the first capacitor and the second capacitor sharing a common top electrode;
- and
- the first and second memory cells each have a total of only one transistor and a total of only one capacitor.
11 more elements
Multiple stacked tiers of memory cells, individual of the tiers of memory cells comprising:
- a first memory cell and a second memory cell laterally adjacent the first memory cell;
- the first memory cell comprising:
- a first capacitor and a first vertical transistor;
- the first vertical transistor comprising a first pillar comprising a channel and an upper source/drain region above the channel of the first vertical transistor, the channel of the first vertical transistor being above and electrically coupled to a digit line;
- and
- the first capacitor comprising a first bottom electrode directly against a lateral side of the upper source/drain region of the first vertical transistor;
- the second memory cell comprising:
- a second capacitor and a second vertical transistor;
- the second vertical transistor comprising a second pillar comprising a channel and an upper source/drain region above the channel of the second vertical transistor, the channel of the second vertical transistor being above and electrically coupled to the digit line;
- and
- the second capacitor comprising a second bottom electrode directly against a lateral side of the upper source drain region of the second vertical transistor;
- and
- the first capacitor and the second capacitor sharing a common top electrode.
10 more elements
Dependencies are inferred from the claim text.