Slew boost disable for an operational amplifier
AssigneeTexas Instruments Incorporated
InventorsMartijn Fridus Snoeij, Steven Graham Brantley
Life of this patent
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Abstract
An operational amplifier includes an input stage configured to receive a first input voltage and a second input voltage and a slew boost circuit coupled to the input stage and configured to selectively increase current through the input stage. The operational amplifier also includes an output stage coupled to the input stage and configured to generate an output voltage, and a slew boost disable circuit configured to assert a control signal to the slew boost circuit to disable the slew boost circuit. The slew boost circuit is disabled when both: the first input voltage being more than a first threshold voltage different from the second input voltage and the output voltage failing to change by more than a second threshold rate.
Claims20
An operational amplifier, comprising:
- an input stage configured to receive a first input voltage and a second input voltage;
- a slew boost circuit coupled to the input stage and configured to selectively increase current through the input stage;
- an output stage coupled to the input stage and configured to generate an output voltage;
- and
- a slew boost disable circuit configured to assert a control signal to the slew boost circuit to disable the slew boost circuit responsive to both:
- the first input voltage being more than a first threshold voltage different from the second input voltage;
- and
- the output voltage failing to change with respect to time by more than a second threshold rate.
A circuit, comprising:
- a first transistor configured to receive a first input voltage;
- a second transistor configured to receive a second input voltage;
- a third transistor coupled to the first transistor and to a first capacitor;
- a fourth transistor coupled to the second transistor and to a second capacitor;
- a fifth transistor coupled to the third and fourth transistors in an arrangement to form a first current mirror with the third transistor and a second current mirror with the fourth transistor;
- and
- a third capacitor coupled to a third current mirror, wherein the third capacitor is configured to receive a third voltage and the third current mirror is coupled to the fifth transistor.
A circuit, comprising:
- a differential input transistor pair configured to receive a first input voltage and a second input voltage;
- a current source coupled to the differential input transistor pair;
- first and second capacitors coupled to the differential input transistor pair;
- a first current mirror coupled to the first capacitor and to a first transistor of the differential input transistor pair;
- a second current mirror coupled to the second capacitor and to a second transistor of the differential input transistor pair;
- and
- a third capacitor coupled to a third current mirror, wherein the third capacitor is configured to receive a third voltage;
- wherein the third current mirror is coupled to the first and second current mirrors;
- and
- wherein a voltage on one of the first or second capacitors is configured to increase responsive to both:
- the first input voltage being more than a first threshold voltage different from the second input voltage;
- and
- the third voltage failing to change by more than a second threshold rate.
Dependencies are inferred from the claim text.