Method of manufacturing a semiconductor die
AssigneeInfineon Technologies Austria AG
InventorsMartin Vielemeyer, Walter Rieger, Martin Pölzl, Gerhard Nöbauer
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Abstract
A method of manufacturing a semiconductor die includes: forming a power HEMT (high-electron-mobility transistor) in a III-nitride semiconductor substrate, the power HEMT having a gate, a source and a drain; monolithically integrating a first gate driver HEMT with the power HEMT in the III-nitride semiconductor substrate, the first gate driver HEMT having a gate, a source and a drain and logically forming part of a driver; and electrically connecting the first gate driver HEMT to the gate of the power HEMT so that the first gate driver HEMT is operable to turn the power HEMT off or on responsive to an externally-generated control signal received from the driver or other device.
Claims15
A method of manufacturing a semiconductor die, the method comprising:
- forming a power HEMT (high-electron-mobility transistor) in a III-nitride semiconductor substrate, the power HEMT having a gate, a source and a drain;
- monolithically integrating a first gate driver HEMT with the power HEMT in the III-nitride semiconductor substrate, the first gate driver HEMT having a gate, a source and a drain and logically forming part of a driver;
- and
- electrically connecting the first gate driver HEMT to the gate of the power HEMT so that the first gate driver HEMT is operable to turn the power HEMT off or on responsive to an externally-generated control signal received from the driver or other device,
- wherein the drain of the first gate driver HEMT is electrically connected to the gate of the power HEMT, and
- wherein the first gate driver is formed as a partial driver circuit such that another part of the driver that the first gate driver logically forms a part of is disposed in a die that is separate from the power HEMT and the first gate driver.
A method of manufacturing a semiconductor die, the method comprising:
- forming a power HEMT (high-electron-mobility transistor) in a III-nitride semiconductor substrate, the power HEMT having a maximum rated gate voltage;
- and
- monolithically integrating a transistor of a gate voltage protection circuit with the power HEMT in the III-nitride semiconductor substrate, the gate voltage protection circuit operable to limit the voltage applied to the gate of the power HEMT to below the maximum rated gate voltage responsive to an externally-generated control signal received at an input terminal of the transistor of the gate voltage protection circuit, the gate voltage protection circuit logically forming part of a driver circuit, another part of the driver circuit being disposed in a die separate from the power HEMT and the first gate driver.
Dependencies are inferred from the claim text.