Stochastic parallel microprocessor

A microprocessor comprising at least one elementary stochastic computation module configured to receive, as input, two random and independent binary input signals each representing a binary coding of two respective given input probability values, and to generate, as output, at least one random binary output signal from the two input signals, said at least one elementary stochastic computation module comprising:

• at least one programmable logic unit, configured to combine the two input signals generate the output signal according to at least one determined logic function, such that the output signal represents a binary coding of an output probability value as a function of the given input probability values;
• at least one addressable memory, configured to store said output probability value coded by the output signal generated by the at least one programmable logic unit;
• at least one first stochastic clock, configured to produce a first random impulse clock signal to control a writing speed, in the at least one addressable memory, of the output probability value coded by the output signal generated by the at least one programmable logic unit;
• and
• at least one second stochastic clock, configured to produce a second random impulse clock signal to control a reading speed of the at least one addressable memory, so as to provide a current evaluation, over a given time window, of the output probability value stored in the at least one addressable memory.