Reduced capacitance land pad
AssigneeIntel Corporation
InventorsZhichao Zhang, Tao Wu, Gaurav Chawla, Jeffrey Lee
Life of this patent
Estimating the term…
Abstract
A land grid array (LGA) land pad having reduced capacitance is disclosed. The conductive portion of a land pad that overlaps a parallel ground plane within the substrate is reduced by one or more non-conductive voids though the thickness of the conductive portion of the land pad. The voids may allow the contact area of the land pad, as defined by the perimeter of the land pad, to remain the same while reducing the conductive portion that overlaps the parallel ground plane. Capacitance between the land pad and the parallel ground plane is reduced by an amount proportional to the reduction in overlapping conductive area.
Claims11
A structure, comprising:
- a substrate having one or more dielectric layers including a conductive trace and a ground plane;
- and
- a plurality of land pads on the surface of the substrate, the land pads each comprising:
- a conductive portion electrically coupled with the conductive trace by one or more vias, the conductive portion having a contact area and a thickness, the contact area for making electrical contact to an individual land grid array (LGA) contact, wherein the contact area is parallel to the ground plane;
- and
- one or more non-conductive voids in the contact area and extending through the thickness of the conductive portion, wherein the conductive portion is continuous around the one or more non-conductive voids.
Dependencies are inferred from the claim text.