Operational disturbance mitigation by controlling word line discharge when an external power supply voltage is reduced during operation of semiconductor memory device

A semiconductor memory device comprising:

• a memory cell array to which a plurality of word lines are coupled;
• a voltage generation circuit configured to apply operating voltages to the plurality of word lines during a program operation;
• and
• a control logic configured to control the voltage generation circuit to perform a discharge operation for the plurality of word lines when an external power supply voltage is reduced during the program operation,
• wherein the control logic controls the voltage generation circuit such that, during the discharge operation,
• a potential level of a selected word line is discharged to potential levels of unselected word lines in a state in which the potential levels of the unselected word lines are maintained, and after the potential level of the selected word line is discharged to the potential levels of the unselected word lines, the potential level of the selected word line and the potential levels of the unselected word lines are simultaneously discharged to a ground level.