FIFO circuit for DDR memory system
AssigneeFaraday Technology Corp.
InventorsChang-Chin Chung, Shen-Chang Wang
Life of this patent
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Abstract
A FIFO circuit for a DDR memory system includes a pointer generator and a FIFO circuit. The FIFO circuit includes a pointer generator and a FIFO buffer. The pointer generator receives a first reset signal and a delay select signal from the memory controller. After the first reset signal is de-asserted, the pointer generator generates a write pointer according to a first reference clock and the pointer generator generates a read pointer according to a second reference clock. An input data is stored into the FIFO buffer according to the first reference clock and the write pointer. An output data is outputted from the FIFO buffer according to the second reference clock and the read pointer.
Claims12
A FIFO circuit connected between a memory controller and a physical layer circuit, the FIFO circuit comprising:
- a pointer generator receiving a first reset signal and a delay select signal from the memory controller, wherein after the first reset signal is de-asserted, the pointer generator generates a write pointer according to a first reference clock and the pointer generator generates a read pointer according to a second reference clock and the delay select signal;
- and
- a FIFO buffer, wherein an input data is stored into the FIFO buffer according to the first reference clock and the write pointer, and an output data is outputted from the FIFO buffer according to the second reference clock and the read pointer;
- wherein the pointer generator comprises:
- a control circuit receiving the first reset signal and the delay select signal, wherein after the control circuit de-asserts the first reset signal, the control circuit de-asserts a second reset signal and then the control circuit de-asserts a third reset signal according to the delay select signal;
- a first ring counter receiving the second reset signal and the first reference clock, wherein when the second reset signal is de-asserted, the first ring counter generates a first counting value as the write pointer according to the first reference clock;
- and a second ring counter receiving the third reset signal and the second reference clock, wherein when the third reset signal is de-asserted, the second ring counter generates a second counting value as the read pointer according to the second reference clock.
A double data rate memory system, comprising:
- a double data rate memory;
- and
- an application-specific integrated circuit connected with the double data rate memory, wherein the application-specific integrated circuit comprises a FIFO circuit, and the FIFO circuit is connected between a memory controller and a physical layer circuit, wherein the FIFO circuit comprises:
- a pointer generator receiving a first reset signal and a delay select signal from the memory controller, wherein after the first reset signal is de-asserted, the pointer generator generates a write pointer according to a first reference clock and the pointer generator generates a read pointer according to a second reference clock and the delay select signal;
- and
- a FIFO buffer, wherein an input data is stored into the FIFO buffer according to the first reference clock and the write pointer, and an output data is outputted from the FIFO buffer according to the second reference clock and the read pointer;
- wherein the pointer generator comprises:
- a control circuit receiving the first reset signal and the delay select signal, wherein after the control circuit de-asserts the first reset signal, the control circuit de-asserts a second reset signal and then the control circuit de-asserts a third reset signal according to the delay select signal;
- a first ring counter receiving the second reset signal and the first reference clock, wherein when the second reset signal is de-asserted, the first ring counter generates a first counting value as the write pointer according to the first reference clock;
- and a second ring counter receiving the third reset signal and the second reference clock, wherein when the third reset signal is de-asserted, the second ring counter generates a second counting value as the read pointer according to the second reference clock.
Dependencies are inferred from the claim text.