Sequential circuit, scan chain circuit including the same and integrated circuit including the same
AssigneeSamsung Electronics Co., Ltd.
InventorTaiki Uemura
Life of this patent
Estimating the term…
Abstract
A sequential circuit includes a data input terminal, a data path, and a redundant feedback loop. The data input terminal receives input data. The data path is connected to the data input terminal and transmits the input data to a data output terminal based on a first clock signal and a second clock signal. The redundant feedback loop is connected to the first data path and stores first data based on at least one of the first or second clock signals when the first data is equal to second data. The first data corresponds to the input data. The second clock signal is a delayed signal of the first clock signal. The second data is delayed data of the first data.
Claims20
A sequential circuit, comprising:
- a data input terminal to receive input data;
- a first data path, connected to the data input terminal, to transmit the input data to a data output terminal based on a first clock signal and a second clock signal;
- and
- a redundant feedback loop, connected to the first data path, to store first data based on at least one of the first or second clock signals when the first data is equal to second data, wherein the first data corresponds to the input data, wherein the second clock signal is a delayed signal of the first clock signal, and wherein the second data is delayed data of the first data.
A scan chain circuit, comprising:
- first through N-th sequential circuits connected in series to sequentially transfer input data based on an input clock signal, where N is a natural number equal to or greater than two, wherein the first sequential circuit includes:
- a data input terminal to receive the input data;
- a first data path, connected to the data input terminal, to transmit the input data to a data output terminal based on a first clock signal and a second clock signal, the first clock signal corresponding to the input clock signal and the second clock signal being a delayed signal of the first clock signal;
- and
- a redundant feedback loop, connected to the first data path, to store first data based on at least one of the first or second clock signals when the first data is equal to second data, wherein the first data corresponds to the input data and wherein the second data is delayed data of the first data.
A circuit, comprising:
- a data path, connected to a data input terminal, to transmit input data to an output terminal based on different clock signals;
- and
- a redundant feedback loop, connected to the data path, to store first data based on at least one of the different clock signals when a difference between the first data and second data is in a predetermined range, wherein the first data corresponds to the input data, wherein a first clock signal of the different clock signals is delayed relative to a second clock signal of the different clock signals, and wherein the second data is delayed data of the first data.
Dependencies are inferred from the claim text.